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Scopus Author ID: 57210339843

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India

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Employment (2)

University of Engineering and Management: Kolkata, West Bengal, IN

2023-08-21 to present | Associate Professor (C.S.E)
Employment
Source: Self-asserted source
Aniruddha Ghosh

Calcutta Institute of Technology: Howrah, West Bengal, IN

2011-01-18 to 2023-08-19 | Assistant Professor (ECE)
Employment
Source: Self-asserted source
Aniruddha Ghosh

Education and qualifications (2)

Maulana Abul Kalam Azad University of Technology, West Bengal: Kolkata, West Bengal, IN

2023-03 | Ph.D (E.C.E)
Qualification
Source: Self-asserted source
Aniruddha Ghosh

West Bengal University of Technology: Kolkata, West Bengal, IN

2007-08-01 to 2009-07-31 | M.E. (Computer Sc. and Engg.)
Education
Source: Self-asserted source
Aniruddha Ghosh

Professional activities (1)

Institution of Engineers India: Kolkata, West Bengal, IN

2019-01-01 to present | CORPORATE (Electronics & Telecommunication)
Membership
Source: Self-asserted source
Aniruddha Ghosh

Works (13)

A DATA HIDING SYSTEM FOR QUALITY ACCESS CONTROL OF GRAYSCALE IMAGE BASED ON FPGA

Republic of South Africa
2023-01-25 | Patent
PAT:

2022/12486
Contributors: Aniruddha Ghosh
Source: Self-asserted source
Aniruddha Ghosh

FPGA-BASED ACCESS CONTROL SYSTEM AND METHOD FORDCT COMPRESSED IMAGES

Australian Patent granted
2021 | Patent
PAT:

2021106217
Source: Self-asserted source
Aniruddha Ghosh

Controlled Chaos Position Transformation and Noise Generation Based Keyless Speech Encryption Technique

International Conference on Computational Intelligence, Data Science and Cloud Computing
2021-12 | Conference paper
Part of DOI: https://doi.org/10.1007/978-981-19-1657-1_29
Source: Self-asserted source
Aniruddha Ghosh

FPGA based MAC units for signal processing algorithms with non-binary numeral system: An effective analysis

2nd Global Conference on Artificial Intelligence and Applications
2021-09 | Conference paper
DOI: https://doi.org/10.1201/9781003269793
Contributors: Aniruddha Ghosh
Source: Self-asserted source
Aniruddha Ghosh

Investigation on Different Performance Parameters under Variable Data Rate Conditions in the Presence of Dispersion Compensation of cost-effective Optical Transport Network

3rd International Conference On Innovations In Communication Computing And Sciences
2021-08 | Conference paper
DOI: https://doi.org/10.1063/5.0105827
Source: Self-asserted source
Aniruddha Ghosh

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

International Journal of Nanoparticles
2020-03 | Journal article
DOI: 10.1504/ijnp.2020.106000
ISSN: 1753-2507
Part of ISSN: 1753-2515
Source: Self-asserted source
Aniruddha Ghosh

Comparative performance analysis of Mixed Number System based MAC unit in various logic domain for signal processing algorithm

International Conference on Sensors and Transducers
2019-04-25 | Conference paper
Source: Self-asserted source
Aniruddha Ghosh

FPGA Implementation of RNS Adder Based MAC Unit in Ternary Value Logic Domain for Signal Processing Algorithm and its Performance Analysis

Proceedings of International Conference on 2018 IEEE Electron Device Kolkata Conference, EDKCON 2018
2018 | Conference paper
DOI: 10.1109/EDKCON.2018.8770463
EID:

2-s2.0-85070361605
Contributors: Ghosh, A.; Sinha, A.
Source: Self-asserted source
Aniruddha Ghosh via Scopus - Elsevier
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Performance Analysis of FPGA Based MAC Unit using DBTNS Multiplier & TRNS Adder for Signal Processing Algorithm

Advances in Image and Video Processing
2018-10-31 | Journal article
DOI: 10.14738/aivp.65.5394
Part of ISSN: 2054-7412
Source: Self-asserted source
Aniruddha Ghosh

FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis

International Journal of Computer Applications
2018-09-17 | Journal article
DOI: 10.5120/ijca2018917785
Part of ISSN: 0975-8887
Source: Self-asserted source
Aniruddha Ghosh

"Floating point RNS"

ACM SIGARCH Computer Architecture News
2012-05-31 | Journal article
DOI: 10.1145/2234336.2234343
Part of ISSN: 0163-5964
Source: Self-asserted source
Aniruddha Ghosh

A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system

ACM SIGARCH Computer Architecture News
2012-05-31 | Journal article
DOI: 10.1145/2234336.2234342
Part of ISSN: 0163-5964
Source: Self-asserted source
Aniruddha Ghosh

A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique

ACM SIGARCH Computer Architecture News
2012-01-09 | Journal article
DOI: 10.1145/2093339.2093343
Part of ISSN: 0163-5964
Source: Self-asserted source
Aniruddha Ghosh

Peer review (11 reviews for 3 publications/grants)

Review activity for Circuits, systems, and signal processing (2)
Review activity for Journal of institution of engineers (India) series B. (7)
Review activity for The journal of supercomputing. (2)
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