Publications

• Public

  Improving performance of codes with large/irregular stride memory access patterns via high performance reconfigurable computers Aug-2012

  DOI: 10.1016/j.jpdc.2012.07.011
  Abed, K & Morris, G, 2012, 'Improving performance of codes with large/irregular stride memory access patterns via high performance reconfigurable computers', Journal of Parallel and Distributed Computing, vol. 27, no. 1–2, p. 3.
• Public

  Mapping a Jacobi Iterative Solver onto a High Performance Heterogeneous Computer 2012

  DOI: 10.1109/TPDS.2012.121
  Morris, G & Abed, K, 2012, 'Mapping a Jacobi Iterative Solver onto a High Performance Heterogeneous Computer', IEEE Transactions on Parallel and Distributed Systems, p. 1.
• Public

  Design Heuristics for Mapping Floating-Point Scientific Computational Kernels onto High Performance Reconfigurable Computers Jun-2009

  DOI: 10.4304/jcp.4.6.542-553
  Rice, J, Abed, K & Morris, G, 2009, 'Design Heuristics for Mapping Floating-Point Scientific Computational Kernels onto High Performance Reconfigurable Computers', Journal of Computers, vol. 4, no. 6.
• Public

  A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS Apr-2009

  DOI: 10.1142/S0218126609005149
  NERURKAR, S & ABED, K, 2009, 'A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS', Journal of Circuits, Systems and Computers, vol. 42, no. 02, pp. 2169-429.
• Public

  LOW POWER DIGITAL DECIMATION FILTER FOR RF WIRELESS COMMUNICATIONS Apr-2008

  DOI: 10.1142/S0218126608004241
  NERURKAR, S & ABED, K, 2008, 'LOW POWER DIGITAL DECIMATION FILTER FOR RF WIRELESS COMMUNICATIONS', Journal of Circuits, Systems and Computers, vol. 8, no. 02, pp. 339-251.
• Public

  Accelerating a Sparse Matrix Iterative Solver Using a High Performance Reconfigurable Computer

  DOI: 10.1109/HPCMP-UGC.2010.30
  Morris, G, McGruder, R & Abed, K, 2010, 'Accelerating a Sparse Matrix Iterative Solver Using a High Performance Reconfigurable Computer', 2010 DoD High Performance Computing Modernization Program Users Group Conference, IEEE, Schaumburg, IL, USA, pp. 517-523.
• Public

  Achieving true parallelism on a High Performance Heterogeneous Computer via a threaded programming model

  DOI: 10.1109/SECON.2011.5752950
  Anderson, A, Morris, G & Abed, K, 2011, 'Achieving true parallelism on a High Performance Heterogeneous Computer via a threaded programming model', 2011 Proceedings of IEEE Southeastcon, IEEE, Nashville, TN, USA, pp. 283-286.
• Public

  CMOS fully differential operational transconductance amplifier design for delta-sigma modulators

  DOI: 10.1109/SECON.2008.4494255
  Nerurkar, S & Abed, K, 2008, 'CMOS fully differential operational transconductance amplifier design for delta-sigma modulators', IEEE SoutheastCon 2008, IEEE, Huntsville, AL, USA, pp. 52-57.
• Public

  Design and Implementation of a Decimation Filter For High Performance Audio Applications

  DOI: 10.1109/ICECS.2007.4511115
  Abed, K, Nerurkar, S & Colaco, S, 2007, 'Design and Implementation of a Decimation Filter For High Performance Audio Applications', 2007 14th IEEE International Conference on Electronics, Circuits and Systems, IEEE, Marrakech, pp. 812-815.
• Public

  FPGA-based implementation of Horner's rule on a high performance heterogeneous computer

  DOI: 10.1109/SECON.2011.5752949
  Malone, A, Morris, G & Abed, K, 2011, 'FPGA-based implementation of Horner's rule on a high performance heterogeneous computer', 2011 Proceedings of IEEE Southeastcon, IEEE, Nashville, TN, USA, pp. 277-282.
• Public

  Implementation of a low-power driver in 65 nanometer CMOS technology

  DOI: 10.1109/SECON.2011.5752940
  Abed, K & Idris, M, 2011, 'Implementation of a low-power driver in 65 nanometer CMOS technology', 2011 Proceedings of IEEE Southeastcon, IEEE, Nashville, TN, USA, pp. 232-236.
• Public

  Improving Performance of Codes with Large/Irregular Stride Memory Access Patterns via High Performance Reconfigurable Computers

  DOI: 10.1109/HPCMP-UGC.2009.70
  Abed, K & Morris, G, 2009, 'Improving Performance of Codes with Large/Irregular Stride Memory Access Patterns via High Performance Reconfigurable Computers', 2009 DoD High Performance Computing Modernization Program Users Group Conference, IEEE, San Diego, CA, USA, pp. 422-429.
• Public

  Integrating Quartus Wizard-based VHDL floating-point components into a high performance heterogeneous computing environment

  DOI: 10.1109/SECON.2011.5752977
  Peay, N, Morris, G & Abed, K, 2011, 'Integrating Quartus Wizard-based VHDL floating-point components into a high performance heterogeneous computing environment', 2011 Proceedings of IEEE Southeastcon, IEEE, Nashville, TN, USA, pp. 413-417.
• Public

  Mapping Hierarchical Multiple File VHDL Kernels onto an SRC-7 High Performance Reconfigurable Computer

  DOI: 10.1109/HPCMP-UGC.2010.31
  Morris, G & Abed, K, 2010, 'Mapping Hierarchical Multiple File VHDL Kernels onto an SRC-7 High Performance Reconfigurable Computer', 2010 DoD High Performance Computing Modernization Program Users Group Conference, IEEE, Schaumburg, IL, USA, pp. 524-533.
• Public

  Reconfigurable computer application design considerations

  DOI: 10.1109/SECON.2008.4494292
  Rice, J, Pace, K, Gates, M, Abed, K, Morris, G & Abed, K, 2008, 'Reconfigurable computer application design considerations', IEEE SoutheastCon 2008, IEEE, Huntsville, AL, USA, pp. 236-243.

Grants

Patents