Personal information

Italy

Activities

Employment (2)

Politecnico di Torino: Torino, Piemonte, IT

2017-07 to present | Post Doc (DAUIN)
Employment
Source: Self-asserted source
Paolo PASINI

Politecnico di Torino: Torino, Piemonte, IT

2013-03 to present | Teacher Assistant (DAUIN)
Employment
Source: Self-asserted source
Paolo PASINI

Education and qualifications (3)

Politecnico di Torino: Torino, Piemonte, IT

2013-03 to 2017-06 | PhD Computer Engineering (Control and Computer Engineering)
Education
Source: Self-asserted source
Paolo PASINI

Politecnico di Torino: Torino, Piemonte, IT

2010 to 2012 | MS Computer Engineering (Control and Computer Engineering)
Education
Source: Self-asserted source
Paolo PASINI

Politecnico di Torino: Torino, Piemonte, IT

2007 to 2010 | BS Computer Engineering (Control and Computer Engineering)
Education
Source: Self-asserted source
Paolo PASINI

Works (7)

NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2025 | Journal article
Contributors: Roberto Bosio; Filippo Minnella; Teodoro Urso; Mario R. Casu; Luciano Lavagno; Mihai T. Lazarescu; Paolo Pasini
Source: check_circle
Crossref

Improving Bounded Model Checking Exploiting Interpolation-Based Learning and Strengthening

IEEE Access
2024 | Journal article
Contributors: Gianpiero Cabodi; Paolo Enrico Camurati; Marco Palena; Paolo Pasini
Source: check_circle
Crossref

Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2024 | Journal article
Contributors: Gianpiero Cabodi; Paolo E. Camurati; Joao Marques-Silva; Marco Palena; Paolo Pasini
Source: check_circle
Crossref

Hardware Model Checking Algorithms and Techniques

Algorithms
2024-06-09 | Journal article
Contributors: Gianpiero Cabodi; Paolo Enrico Camurati; Marco Palena; Paolo Pasini
Source: check_circle
Crossref
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Preferred source (of 2)‎

Reducing Interpolant Circuit Size Through SAT-Based Weakening

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2020-07 | Journal article
Contributors: G. Cabodi; P. E. Camurati; M. Palena; P. Pasini; D. Vendraminetto
Source: check_circle
Crossref

Logic Synthesis for Interpolant Circuit Compaction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2019-02 | Journal article
Contributors: G. Cabodi; P. E. Camurati; M. Palena; P. Pasini; D. Vendraminetto
Source: check_circle
Crossref

Test of Reconfigurable Modules in Scan Networks

IEEE Transactions on Computers
2018-12-01 | Journal article
Contributors: Riccardo Cantoro; Farrokh Ghani Zadegan; Marco Palena; Paolo Pasini; Erik Larsson; Matteo Sonza Reorda
Source: check_circle
Crossref