Personal information

Taiwan

Activities

Employment (1)

Taiwan Semiconductor Manufacturing Company: Hsinchu, TW

2005-01-01 to present
Employment
Source: Self-asserted source
TsungHsien Tsai

Education and qualifications (1)

National Chung Cheng University: Minhsiung, TW

2002-07-01 to 2004-09-30
Education
Source: Self-asserted source
TsungHsien Tsai

Works (27)

A 55.9-fs Integrated Jitter (100 kHz–100 MHz) Hybrid LC-Tank PLL in 5-nm FinFET Using Programmable Phase Realignment and Dynamic Coarse Tuning

IEEE Solid-State Circuits Letters
2021 | Journal article
Contributors: Tsung-Hsien Tsai; Ruey-Bin Sheen; Sheng-Yun Hsu; Chih-Hsien Chang; R. Bogdan Staszewski
Source: check_circle
Crossref

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

IEEE Transactions on Circuits and Systems I: Regular Papers
2021-05 | Journal article
Contributors: Chao-Chieh Li; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Yu-Tso Lin; Tsung-Hsien Tsai; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo et al.
Source: check_circle
Crossref

A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and −240.5-dB FoM in 7-nm FinFET

IEEE Solid-State Circuits Letters
2020 | Journal article
Contributors: Tsung-Hsien Tsai; Ruey-Bin Sheen; Chih-Hsien Chang; Kenny Cheng-Hsiang Hsieh; Robert Bogdan Staszewski
Source: check_circle
Crossref

A 0.2 GHz to 4GHz hybrid PLL (ADPLL/charge-pump-PLL) in 7NM FinFET CMOS featuring 0.619 PS integrated jitter and 0.6 US settling time at 2.3 MW

2018 IEEE Symposium on VLSI Circuits
2018-06-08 | Conference paper
Source: Self-asserted source
TsungHsien Tsai

A 0.034mm2, 725fs rms jitter, 1.8%/V frequency-pushing, 10.8–19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS

Conference paper
Source: Self-asserted source
TsungHsien Tsai

A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

Conference paper
Source: Self-asserted source
TsungHsien Tsai

US Patent 7,786,771: Phase lock loop (PLL) with gain control

Source: Self-asserted source
TsungHsien Tsai

US Patent 7,791,420: Phase-locked loop with start-up circuit

Registered copyright
Source: Self-asserted source
TsungHsien Tsai

US Patent 8,013,657: Temperature compensated integrator

Source: Self-asserted source
TsungHsien Tsai

US Patent 8,183,914: Constant Gm circuit and methods

Source: Self-asserted source
TsungHsien Tsai

US Patent 8,314,652: System and method for RC calibration using phase and frequency

Source: Self-asserted source
TsungHsien Tsai

US Patent 8,589,831: Skew sensitive calculation for misalignment from multi patterning

Registered copyright
Source: Self-asserted source
TsungHsien Tsai

US Patent 8,847,572: Optimization methodology and apparatus for wide-swing current mirror with wide current range

Registered copyright
Source: Self-asserted source
TsungHsien Tsai

US Patent 9,112,507: Phase-locked loop start up circuit

Source: Self-asserted source
TsungHsien Tsai

US Patent 9,148,135: Real time automatic and background calibration at embedded duty cycle correlation

Source: Self-asserted source
TsungHsien Tsai

US Patent 9,219,471: Circuitry for phase detector

Source: Self-asserted source
TsungHsien Tsai

US Patent 9,229,050: BIST circuit for phase measurement

Source: Self-asserted source
TsungHsien Tsai

US Patent 9,257,998: Phase locked loop

Source: Self-asserted source
TsungHsien Tsai

US Patent 9,270,290: Masking circuit and time-to-digital converter comprising the same

Source: Self-asserted source
TsungHsien Tsai

US Patent 9,369,134: PLL with across-stage controlled DCO

Source: Self-asserted source
TsungHsien Tsai

US Patent 9,379,718: All-digital phase-locked loop (ADPLL)

Source: Self-asserted source
TsungHsien Tsai

US Patent 9,425,773: Digital control ring oscillator and method of assembling same

Source: Self-asserted source
TsungHsien Tsai

US Patent 9,496,882: Digitally controlled oscillator

Source: Self-asserted source
TsungHsien Tsai

US Patent 9,621,171: Frequency scaling method, circuit and associated all-digital phase-locked loop

Registered copyright
Source: Self-asserted source
TsungHsien Tsai

US Patent 9,837,994: Stacked delay element and method of assembling same

Registered copyright
Source: Self-asserted source
TsungHsien Tsai

US Patent 9,853,807: Automatic detection of change in PLL locking trend

Source: Self-asserted source
TsungHsien Tsai

US Patent 9,893,680: Regulating cascode circuit with self-calibration capability

Registered copyright
Source: Self-asserted source
TsungHsien Tsai