Personal information

No personal information available

Activities

Employment (1)

National Institute of Technology Karnataka: Surathkal, Karnataka, IN

2015-07-08 to present | RESEARCH SCHOLAR (ELECTRONICS AND COMMUNICATION)
Employment
Source: Self-asserted source
sreenivasulu polineni

Education and qualifications (3)

National Institute of Technology Karnataka: Surathkal, Karnataka, IN

2015-07-08 to present | Ph.D. (ELECTRONICS & COMMUNICATIONS)
Education
Source: Self-asserted source
sreenivasulu polineni

National Institute of Technology Kurukshetra: Kurukshetra, Haryana, IN

2013-07-21 to 2015-06-30 | M.Tech (School of VLSI Design & Embedded system design)
Education
Source: Self-asserted source
sreenivasulu polineni

Jawaharlal Nehru Technological University - ANANTAPUR: ANANTAPUR, ANDHRA PRADESH, IN

2009-09-17 to 2013-05-15 | B.Tech (Electronics and Communication Engineering)
Education
Source: Self-asserted source
sreenivasulu polineni

Works (10)

A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications

IET Circuits, Devices & Systems
2021-01-12 | Journal article
Part of ISSN: 1751-858X
Part of ISSN: 1751-8598
Source: Self-asserted source
sreenivasulu polineni

A 0.3‐V, 2.4‐nW, and 100‐Hz fourth‐order LPF for ECG signal processing

International Journal of Circuit Theory and Applications
2020-11 | Journal article
Part of ISSN: 0098-9886
Part of ISSN: 1097-007X
Source: Self-asserted source
sreenivasulu polineni

A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique

Circuits, Systems, and Signal Processing
2020-11 | Journal article
Part of ISSN: 0278-081X
Part of ISSN: 1531-5878
Source: Self-asserted source
sreenivasulu polineni

Ultra Low-Voltage, Low-Power Fourth-Order Butterworth LPF for ECG Signal Processing

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)
2020-07 | Conference paper
Source: Self-asserted source
sreenivasulu polineni

A 10-Bit Differential Ultra-Low-Power SAR ADC with an Enhanced MSB Capacitor-Split Switching Technique

Arabian Journal for Science and Engineering
2019 | Journal article
Source: Self-asserted source
sreenivasulu polineni

A 0.3 V, 56 dB DR, 100 Hz fourth order low-pass filter for ECG acquisition system

Microelectronics Journal
2019-12 | Journal article
Part of ISSN: 0026-2692
Source: Self-asserted source
sreenivasulu polineni

Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology

2019 9th International Symposium on Embedded Computing and System Design (ISED)
2019-12 | Conference paper
Source: Self-asserted source
sreenivasulu polineni

91dB Dynamic Range 9.5nW Low Pass Filter for Bio-Medical Applications

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
2018 | Conference paper
Source: Self-asserted source
sreenivasulu polineni

A Three-Stage Operational Transconductance Amplifier for Delta Sigma Modulator

2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)
2018 | Conference paper
Source: Self-asserted source
sreenivasulu polineni
grade
Preferred source (of 2)‎

8-bit Nano watt level crossing ADC for bio-medical application

IEEE International Conference on Computer Communication and Control, IC4 2015
2016-09 | Conference paper
Part of ISBN: 9781479981649
Source: Self-asserted source
sreenivasulu polineni
grade
Preferred source (of 3)‎