Personal information

Other IDs

ResearcherID: L-8849-2014

Keywords

Low power VLSI, Low power adder,low power multiplier

Countries

India

Activities

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Employment (1)

Nandha College of Technology: Erode, Tamilnadu, IN

2010-07-07 to 2020-04-23 | Associate professor (ECE)
Employment
Source: Self-asserted source
Kesavan S.P.

Education and qualifications (1)

KSR College of Technology: Thiruchengode, Namakkal ,tamilnadu, IN

2006-08-02 to 2008-06-06 | M.E (VLSI DESIGN) (ECE)
Education
Source: Self-asserted source
Kesavan S.P.

Works (1)

FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic

International Journal of Circuit Theory and Applications
2020-08 | Journal article
DOI: 10.1002/cta.2794
Contributors: Kesavan Subannan Palanisamy; Rajeswari Ramachandran
Source: check_circle
Crossref
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