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Education and qualifications (1)

Ulsan National Institute of Science and Technology: Ulsan, Ulsan, KR

2015-02-01 to present | Combined MS/Ph.D Degree (Electrical Engineering)
Education
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Taeho Seong

Works (8)

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

IEEE Journal of Solid-State Circuits
2018-04 | Journal article
DOI: 10.1109/jssc.2017.2768411
Part of ISSN: 0018-9200
Contributors: Yongsun Lee; Taeho Seong; Seyeon Yoo; Jaehyouk Choi
Source: Self-asserted source
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A −242dB FOM and −75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC

2018 IEEE International Solid - State Circuits Conference - (ISSCC)
2018-02 | Conference paper
DOI: 10.1109/isscc.2018.8310351
Part of ISBN: 9781509049400
Contributors: Taeho Seong; Yongsun Lee; Seyeon Yoo; Jaehyouk Choi
Source: Self-asserted source
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A −242-dB FOM and −71-dBc reference spur ring-VCO-based ultra-low-jitter switched-loop-filter PLL using a fast phase-error correction technique

2017 Symposium on VLSI Circuits
2017-06 | Conference paper
DOI: 10.23919/vlsic.2017.8008476
Part of ISBN: 9784863486140
Contributors: Taeho Seong; Yongsun Lee; Seyeon Yoo; Jaehyouk Choi
Source: Self-asserted source
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A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells

IEEE Journal of Solid-State Circuits
2016-02 | Journal article
DOI: 10.1109/jssc.2015.2496781
Part of ISSN: 0018-9200
Source: Self-asserted source
Taeho Seong via Crossref Metadata Search

An Ultra-Low Power and Compact LC-Tank-Based Frequency Tripler Using Pulsed Input Signals

IEEE Microwave and Wireless Components Letters
2016-02 | Journal article
DOI: 10.1109/lmwc.2016.2517136
Part of ISSN: 1531-1309
Contributors: Seyeon Yoo; Seojin Choi; Taeho Seong; Jaehyouk Choi
Source: Self-asserted source
Taeho Seong via Crossref Metadata Search

A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for <formula formulatype="inline"><tex Notation="TeX">$\Delta\Sigma$</tex></formula> PLLs

IEEE Transactions on Circuits and Systems I: Regular Papers
2015-03 | Journal article
DOI: 10.1109/tcsi.2014.2370191
Part of ISSN: 1549-8328
Contributors: Yongsun Lee; Mina Kim; Taeho Seong; Jaehyouk Choi
Source: Self-asserted source
Taeho Seong via Crossref Metadata Search

Analysis and Design of a Core-Size-Scalable Low Phase Noise <formula formulatype="inline"><tex Notation="TeX">$LC$</tex> </formula>-VCO for Multi-Standard Cellular Transceivers

IEEE Transactions on Circuits and Systems I: Regular Papers
2015-03 | Journal article
DOI: 10.1109/tcsi.2014.2382191
Part of ISSN: 1549-8328
Contributors: Taeho Seong; Jae Joon Kim; Jaehyouk Choi
Source: Self-asserted source
Taeho Seong via Crossref Metadata Search

Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration

IEEE Transactions on Circuits and Systems II: Express Briefs
2014-09 | Journal article
DOI: 10.1109/tcsii.2014.2335435
Part of ISSN: 1549-7747
Contributors: Taeho Seong; Yongsun Lee; Jaehyouk Choi
Source: Self-asserted source
Taeho Seong via Crossref Metadata Search
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