Personal information

India

Activities

Employment (1)

National Institute of Technology: Calicut, Kerala, IN

1986-05-23 to present | Professor (Computer Science and Engineering)
Employment
Source: Self-asserted source
Vineeth Paleri

Education and qualifications (3)

Indian Institute of Science: Bangalore, Karnataka, IN

1994 to 1999 | PhD (Computer Science and Automation)
Education
Source: Self-asserted source
Vineeth Paleri

Indian Institute of Technology Kanpur: Kanpur, Uttar Pradesh, IN

1984-08-01 to 1986-02-15 | MTech (Computer Science and Engineering)
Education
Source: Self-asserted source
Vineeth Paleri

National Institute of Technology: Calicut, Kerala, IN

1976 to 1981 | BSc(Engg.) (Electrical Engineering)
Education
Source: Self-asserted source
Vineeth Paleri

Works (4)

An improved algorithm for redundancy detection using global value numbering

Journal of Information Processing Systems
2016 | Journal article
EID:

2-s2.0-85018529843

Contributors: Saleena, N.; Paleri, V.
Source: Self-asserted source
Vineeth Paleri via Scopus - Elsevier

Global value numbering for redundancy detection: A simple and efficient algorithm

Proceedings of the ACM Symposium on Applied Computing
2014 | Conference paper
EID:

2-s2.0-84905644145

Contributors: Saleena, N.; Paleri, V.
Source: Self-asserted source
Vineeth Paleri via Scopus - Elsevier

Partial redundancy elimination: A simple, pragmatic, and provably correct algorithm

Science of Computer Programming
2003 | Journal article
EID:

2-s2.0-0038519833

Contributors: Paleri, V.K.; Srikant, Y.N.; Shankar, P.
Source: Self-asserted source
Vineeth Paleri via Scopus - Elsevier

A Simple Algorithm for Partial Redundancy Elimination

SIGPLAN Notices (ACM Special Interest Group on Programming Languages)
1998 | Journal article
EID:

2-s2.0-0037622742

Contributors: Paleri, V.K.; Srikant, Y.N.; Shankar, P.
Source: Self-asserted source
Vineeth Paleri via Scopus - Elsevier