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Employment (1)

Indian Institute of Technology Mandi: Mandi, Himachal Pradesh, IN

2018-02-01 to 2023-01-31 | Ph.D. Research Scholar (School of Computing and Electrical Engineering (SCEE))
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ANUJ VERMA

Professional activities (1)

IEEE: New York, NY, US

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ANUJ VERMA

Works (5)

High-Throughput and Hardware-Efficient ASIC-Chip Fabrication of Reconfigurable LDPC/Polar Decoder for mMTC and URLLC 5G-NR Applications

IEEE Transactions on Circuits and Systems I: Regular Papers
2024 | Journal article
DOI: 10.1109/TCSI.2024.3429174
Contributors: Anuj Verma; Rahul Shrestha
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Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes

IEEE Transactions on Vehicular Technology
2023-01 | Journal article
DOI: 10.1109/TVT.2022.3203802
Contributors: Anuj Verma; Rahul Shrestha
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Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture

IEEE Transactions on Circuits and Systems II: Express Briefs
2021-08 | Journal article
DOI: 10.1109/TCSII.2021.3071804
Contributors: Anuj Verma; Rahul Shrestha
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Crossref

A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard

2020 IEEE International Symposium on Circuits and Systems (ISCAS)
2020-10 | Conference paper
DOI: 10.1109/iscas45731.2020.9181188
Contributors: ANUJ VERMA
Source: Self-asserted source
ANUJ VERMA

A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio

2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)
2020-01 | Conference paper
DOI: 10.1109/vlsid49098.2020.00018
Contributors: ANUJ VERMA
Source: Self-asserted source
ANUJ VERMA
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