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ResearcherID: KHX-9776-2024

Keywords

wireless communication, VLSI, ASIC, application specific integrated circuits, digital circuits, digital signal processing, error correction codes, LDPC, Turbo code, convolutional code, polar code, configurable FEC decoder, forward error correction, communication system, 5G, satellite communication, integrated circuits, algorithm hardware co-optimization, channel coding

Countries

United States

Biography

I am a PhD candidate at University of Michigan. My research area includes ASIC design for configurable FEC decoders, CGRA design, digital circuits for wireless communication, ASIC accelerator for neural networks, low power circuits.

Activities

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Education and qualifications (2)

University of Michigan–Ann Arbor: Ann Arbor, Michigan, US

2020-09-01 to 2025-12-31 | PhD (Electrical and Computer Engineering)
Education
Source: Self-asserted source
Yufan Yue

University of Michigan - Ann Arbor: Ann Arbor, MI, US

2018-09-01 to 2020-04-30 | Bachlor (Electrical engineering and computer science)
Education
Source: Self-asserted source
Yufan Yue

Works (8)

DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET

IEEE Journal of Solid-State Circuits
2025-02 | Journal article
DOI: 10.1109/JSSC.2024.3438758
Contributors: Kuan-Yu Chen; Chi-Sheng Yang; Yu-Hsiu Sun; Chien-Wei Tseng; Morteza Fayazi; Xin He; Siying Feng; Yufan Yue; Trevor Mudge; Ronald Dreslinski et al.
Source: check_circle
Crossref

A 33.06-Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Intersatellite Communication

IEEE Solid-State Circuits Letters
2024 | Journal article
DOI: 10.1109/LSSC.2024.3486234
Contributors: Xiangdong Wei; Yufan Yue; Seungkyu Choi; Tutu Ajayi; Ronald Dreslinski; David Blaauw; Hun-Seok Kim
Source: check_circle
Crossref

ParaBase: A Configurable Parallel Baseband Processor for Ultra-High-Speed Inter-Satellite Optical Communications

2024-08-05 | Conference paper
DOI: 10.1145/3665314.3673174
Contributors: Seungkyu Choi; Huanshihong Deng; Kuan-Yu Chen; Yufan Yue; David Blaauw; Hun Seok Kim
Source: check_circle
Crossref

A Fully Configurable Unified FEC Decoder for LDPC, Polar, Turbo, and Convolutional Codes with Row-First Collision-Free Compression

2024-04-09 | Preprint | Author
DOI: 10.36227/techrxiv.171262833.36139863/v1
Contributors: Yufan Yue; Seungkyu Choi; Tutu Ajayi; Xiangdong Wei; Ronald Dreslinski; David Blaauw; Hun Seok Kim
Source: Self-asserted source
Yufan Yue
grade
Preferred source (of 2)‎

A 507 GMACs/J 256-core domain adaptive systolic-array-processor for wireless communication and linear-algebra kernels in 12nm FINFET

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
2022 | Conference paper
Contributors: Chen, Kuan-Yu; Yang, Chi-Sheng; Sun, Yu-Hsiu; Tseng, Chien-Wei; Fayazi, Morteza; He, Xin; Feng, Siying; Yue, Yufan; Mudge, Trevor; Dreslinski, Ronald et al.
Source: Self-asserted source
Yufan Yue

A unified forward error correction accelerator for multi-mode Turbo, LDPC, and polar decoding

Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design
2022 | Conference paper
Contributors: Yue, Yufan; Ajayi, Tutu; Liu, Xueyang; Xing, Peiwen; Wang, Zihan; Blaauw, David; Dreslinski, Ronald; Kim, Hun Seok
Source: Self-asserted source
Yufan Yue

A Unified Forward Error Correction Accelerator for Multi-Mode Turbo, LDPC, and Polar Decoding

International Symposium on Low Power Electronics and Design - ISLPED
2022 | Conference paper
DOI: 10.1145/3531437.3539726
WOSUID: WOS:001124259000028
Contributors: Yue, Yufan; Ajayi, Tutu; Liu, Xueyang; Xing, Peiwen; Wang, Zihan; Blaauw, David; Dreslinski, Ron; Kim, Hun-Seok
Source: check_circle
Web of Science Researcher Profile Sync

Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor

2022 IEEE International Symposium on Circuits and Systems (ISCAS)
2022 | Conference paper
Contributors: Bliss, Daniel W; Ajayi, Tutu; Akoglu, Ali; Aliyev, I; Basaklar, Toygun; Belayneh, Leul; Blaauw, D; Brunhaver, John; Chakrabarti, Chaitali; Chang, Liangliang et al.
Source: Self-asserted source
Yufan Yue

Peer review (51 reviews for 9 publications/grants)

Review activity for Digital signal processing. (16)
Review activity for IEEE signal processing letters. (1)
Review activity for IEEE solid-state circuits letters. (2)
Review activity for IEEE transactions on circuits and systems. (9)
Review activity for IEEE transactions on circuits and systems. (8)
Review activity for IEEE transactions on very large scale integration (VLSI) systems. (6)
Review activity for Journal of systems architecture. (1)
Review activity for Nano communication networks. (2)
Review activity for Physical communication. (6)
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