Cancio MONTEIRO (0000-0002-5264-2326)

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Universidade Nacional Timor Lorasa'e: Dili, Dili, TL

2006-07-01 to present | Senior Lecturer (Electronics and Electrical Engineering )

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Cancio MONTEIRO

Gifu University: Gifu City, Gifu-Ken, JP

2012 to 2015-03-25 | Ph.D. (Graduate School of Engineering )

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Cancio MONTEIRO

Gifu University: Gifu City, Gifu -Ken, JP

2010-04-06 to 2012-03-25 | M.Eng, (Graduate School of Engineering )

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Cancio MONTEIRO

Universidade Nacional Timor Lorasa'e: Dili, Dili, TL

2002-10-02 to 2005-07-30 | Diploma-3 (Electronics and Electrical Engineering )

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Cancio MONTEIRO

Low-Power Two-Phase Clocking Adiabatic PUF Circuit

Electronics

2021 | Journal article

DOI: 10.3390/electronics10111258

Part of ISSN: 2079-9292

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Cancio MONTEIRO

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Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices

Sensors

2021-12 | Journal article | Author

DOI: 10.3390/s21248302

Contributors: Cancio MONTEIRO; Yasuhiro Takahashi

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Multidisciplinary Digital Publishing Institute

Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices

2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

2018-11 | Conference paper

DOI: 10.1109/ispacs.2018.8923180

ISBN: 9781538657713

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Cancio MONTEIRO

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Charge-Sharing Symmetric Adiabatic Logic: Comparative Analysis, Application and LSI Implementation for Cryptographic Hardware Design ; 負荷容量均一化対称構造断熱的論理回路～暗号ハードウェア設計のための比較解析、応用およびLSI実装～

2015 | Dissertation or Thesis

URI:

http://hdl.handle.net/20.500.12099/51034

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Cancio MONTEIRO

Low‐power secure S‐box circuit using charge‐sharing symmetric adiabatic logic for advanced encryption standard hardware design

IET Circuits, Devices & Systems

2015-09 | Journal article

DOI: 10.1049/iet-cds.2014.0150

Part of ISSN: 1751-858X

Part of ISSN: 1751-8598

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Cancio MONTEIRO

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Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

2014-11 | Conference paper

DOI: 10.1109/apccas.2014.7032734

ISBN: 9781479952304

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Cancio MONTEIRO

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Process variation verification of low-power secure CSSAL AES S-box circuit

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

2014-08 | Conference paper

DOI: 10.1109/mwscas.2014.6908342

ISBN: 9781479941322

ISBN: 9781479941346

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Cancio MONTEIRO

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An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

2014-06 | Conference paper

DOI: 10.1109/iscas.2014.6865263

Part of ISBN: 9781479934324

Part of ISBN: 9781479934317

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Cancio MONTEIRO

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Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

International Journal of Modeling and Optimization

2013 | Journal article

DOI: 10.7763/ijmo.2013.v3.292

Part of ISSN: 2010-3697

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Cancio MONTEIRO

Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology

2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings

2013 | Conference paper

EID:

2-s2.0-84892657017

Contributors: Monteiro, C.; Takahashi, Y.; Sekine, T.

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Cancio MONTEIRO via Scopus - Elsevier

Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology

2013 European Conference on Circuit Theory and Design (ECCTD)

2013-09 | Conference paper

DOI: 10.1109/ecctd.2013.6662327

ISBN: 9783000437854

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Cancio MONTEIRO

Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks

2013 36th International Conference on Telecommunications and Signal Processing (TSP)

2013-07 | Conference paper

DOI: 10.1109/tsp.2013.6614034

ISBN: 9781479904044

ISBN: 9781479904020

ISBN: 9781479904037

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Cancio MONTEIRO

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Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level

Microelectronics Journal

2013-06 | Journal article

DOI: 10.1016/j.mejo.2013.04.003

Part of ISSN: 0026-2692

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Cancio MONTEIRO

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Low power secure AES S-box using adiabatic logic circuit

2013 IEEE Faible Tension Faible Consommation

2013-06 | Conference paper

DOI: 10.1109/ftfc.2013.6577751

ISBN: 9781467361040

ISBN: 9781467361057

ISBN: 9781467361033

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Cancio MONTEIRO

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DPA resistance of charge-sharing symmetric adiabatic logic

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

2013-05 | Conference paper

DOI: 10.1109/iscas.2013.6572406

ISBN: 9781467357623

ISBN: 9781467357609

ISBN: 9781467357616

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Cancio MONTEIRO

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Low Power CSSAL Bit-Parallel Multiplier over GF(2^4) in 0.18μm CMOS Technology

IEICE technical report. Electromagnetic compatibility

2013-04 | Journal article

Part of ISSN: 0913-5685

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Cancio MONTEIRO

Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card

2011 International Symposium on Intelligent Signal Processing and Communications Systems (ISPACS)

2011-12 | Conference paper

DOI: 10.1109/ispacs.2011.6146067

ISBN: 9781457721663

ISBN: 9781457721656

ISBN: 9781457721649

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Cancio MONTEIRO

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Cancio MONTEIRO

https://orcid.org/0000-0002-5264-2326

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Employment (1)

Universidade Nacional Timor Lorasa'e: Dili, Dili, TL

Education and qualifications (3)

Gifu University: Gifu City, Gifu-Ken, JP

Gifu University: Gifu City, Gifu -Ken, JP

Universidade Nacional Timor Lorasa'e: Dili, Dili, TL

Works (17)

Low-Power Two-Phase Clocking Adiabatic PUF Circuit

Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices

Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices

Charge-Sharing Symmetric Adiabatic Logic: Comparative Analysis, Application and LSI Implementation for Cryptographic Hardware Design ; 負荷容量均一化対称構造断熱的論理回路～暗号ハードウェア設計のための比較解析、応用およびLSI実装～

Low‐power secure S‐box circuit using charge‐sharing symmetric adiabatic logic for advanced encryption standard hardware design

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation

Process variation verification of low-power secure CSSAL AES S-box circuit

An LSI implementation of a bit-parallel cellular multiplier over GF(2<sup>4</sup>) using secure charge-sharing symmetric adiabatic logic

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

Low power secure CSSAL bit-parallel multiplier over GF(2<sup>4</sup>) in 0.18μm CMOS technology

Low power secure CSSAL bit-parallel multiplier over GF(2<sup>4</sup>) in 0.18μm CMOS technology

Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks

Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level

Low power secure AES S-box using adiabatic logic circuit

DPA resistance of charge-sharing symmetric adiabatic logic

Low Power CSSAL Bit-Parallel Multiplier over GF(2^4) in 0.18μm CMOS Technology

Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card

Cancio MONTEIRO

https://orcid.org/0000-0002-5264-2326

Personal information

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Verified email domains

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Employment (1)

Universidade Nacional Timor Lorasa'e: Dili, Dili, TL

Education and qualifications (3)

Gifu University: Gifu City, Gifu-Ken, JP

Gifu University: Gifu City, Gifu -Ken, JP

Universidade Nacional Timor Lorasa'e: Dili, Dili, TL

Works (17)

Low-Power Two-Phase Clocking Adiabatic PUF Circuit

Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices

Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices

Charge-Sharing Symmetric Adiabatic Logic: Comparative Analysis, Application and LSI Implementation for Cryptographic Hardware Design ; 負荷容量均一化対称構造断熱的論理回路 ～暗号ハードウェア設計のための比較解析、応用およびLSI実装～

Low‐power secure S‐box circuit using charge‐sharing symmetric adiabatic logic for advanced encryption standard hardware design

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation

Process variation verification of low-power secure CSSAL AES S-box circuit

An LSI implementation of a bit-parallel cellular multiplier over GF(2<sup>4</sup>) using secure charge-sharing symmetric adiabatic logic

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

Low power secure CSSAL bit-parallel multiplier over GF(2<sup>4</sup>) in 0.18μm CMOS technology

Low power secure CSSAL bit-parallel multiplier over GF(2<sup>4</sup>) in 0.18&#x03BC;m CMOS technology

Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks

Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level

Low power secure AES S-box using adiabatic logic circuit

DPA resistance of charge-sharing symmetric adiabatic logic

Low Power CSSAL Bit-Parallel Multiplier over GF(2^4) in 0.18μm CMOS Technology

Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card

Charge-Sharing Symmetric Adiabatic Logic: Comparative Analysis, Application and LSI Implementation for Cryptographic Hardware Design ; 負荷容量均一化対称構造断熱的論理回路～暗号ハードウェア設計のための比較解析、応用およびLSI実装～

Low power secure CSSAL bit-parallel multiplier over GF(2<sup>4</sup>) in 0.18μm CMOS technology