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Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

IEEE Access
2020 | Journal article
Contributors: Nguyen My Qui; Chang Hong Lin; Poki Chen
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High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2020-04 | Journal article
Contributors: Poki Chen; Jian-Ting Lan; Ruei-Ting Wang; Nguyen My Qui; John Carl Joel S. Marquez; Seiji Kajihara; Yousuke Miyake
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