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Keywords

compilers, computer systems, programming languages

Countries

China, United States

Biography

Hongzheng Chen is currently a Ph.D. student at Cornell University. He received his B.E. degree from Sun Yat-sen University, Guangzhou, China. His research interests include domain-specific languages and compilers.

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Education and qualifications (2)

Cornell University: Ithaca, New York, US

2021-08-26 to present | Ph.D. (Computer Science)
Education
Source: Self-asserted source
Hongzheng Chen

Sun Yat-sen University: Guangzhou, Guangdong, CN

2017-09-01 to 2021-07-01 (School of Computer Science and Engineering)
Education
Source: Self-asserted source
Hongzheng Chen

Works (16)

Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference

ACM Transactions on Reconfigurable Technology and Systems
2025-03-31 | Journal article
DOI: 10.1145/3656177
Contributors: Hongzheng Chen; Jiahao Zhang; Yixiao Du; Shaojie Xiang; Zichao Yue; Niansong Zhang; Yaohui Cai; Zhiru Zhang
Source: check_circle
Crossref

ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines

2025-02-27 | Conference paper
DOI: 10.1145/3706628.3708870
Contributors: Jinming Zhuang; Shaojie Xiang; Hongzheng Chen; Niansong Zhang; Zhuoping Yang; Tony Mao; Zhiru Zhang; Peipei Zhou
Source: check_circle
Crossref

Allo: A Programming Model for Composable Accelerator Design

arXiv
2024 | Journal article
DOI: 10.48550/ARXIV.2404.04815
Contributors: Hongzheng Chen; Niansong Zhang; Shaojie Xiang; Zhichen Zeng; Mengjia Dai; Zhiru Zhang
Source: Self-asserted source
Hongzheng Chen

Allo: A Programming Model for Composable Accelerator Design

Proceedings of the ACM on Programming Languages
2024-06-20 | Journal article
DOI: 10.1145/3656401
Contributors: Hongzheng Chen; Niansong Zhang; Shaojie Xiang; Zhichen Zeng; Mengjia Dai; Zhiru Zhang
Source: check_circle
Crossref

A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs

2024-04 | Conference paper
DOI: 10.1145/3626202.3637600
Contributors: Hongzheng Chen; Jiahao Zhang; Yixiao Du; Shaojie Xiang; Zichao Yue; Niansong Zhang; Yaohui Cai; Zhiru Zhang
Source: check_circle
Crossref

Formal Verification of Source-to-Source Transformations for HLS

2024-04 | Conference paper
DOI: 10.1145/3626202.3637563
Contributors: Louis-Noël Pouchet; Emily Tucker; Niansong Zhang; Hongzheng Chen; Debjit Pal; Gabriel Rodríguez; Zhiru Zhang
Source: check_circle
Crossref

Slapo: A Schedule Language for Progressive Optimization of Large Deep Learning Model Training

2024-04-27 | Conference paper
DOI: 10.1145/3620665.3640399
Contributors: Hongzheng Chen; Cody Hao Yu; Shuai Zheng; Zhen Zhang; Zhiru Zhang; Yida Wang
Source: check_circle
Crossref

Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference

2023 | Journal article
DOI: 10.48550/ARXIV.2312.15159
Contributors: Hongzheng Chen; Jiahao Zhang; Yixiao Du; Shaojie Xiang; Zichao Yue; Niansong Zhang; Yaohui Cai; Zhiru Zhang
Source: Self-asserted source
Hongzheng Chen

Structured Pruning is All You Need for Pruning CNNs at Initialization

2022 | Preprint
DOI: 10.48550/ARXIV.2203.02549
Source: Self-asserted source
Hongzheng Chen

Accelerator design with decoupled hardware customizations

Proceedings of the 59th ACM/IEEE Design Automation Conference
2022-07-10 | Conference paper
DOI: 10.1145/3489517.3530681
Contributors: Debjit Pal; Yi-Hsiang Lai; Shaojie Xiang; Niansong Zhang; Hongzheng Chen; Jeremy Casas; Pasquale Cocchini; Zhenkun Yang; Jin Yang; Louis-Noël Pouchet et al.
Source: Self-asserted source
Hongzheng Chen

HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
2022-02-13 | Conference paper
DOI: 10.1145/3490422.3502369
Source: Self-asserted source
Hongzheng Chen

BGL: GPU-Efficient GNN Training by Optimizing Graph Data I/O and Preprocessing

2021 | Preprint
DOI: 10.48550/ARXIV.2112.08541
Source: Self-asserted source
Hongzheng Chen

Krill: A Compiler and Runtime System for Concurrent Graph Processing

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC)
2021-11-14 | Conference paper
DOI: 10.1145/3458817.3476159
Source: Self-asserted source
Hongzheng Chen

FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations

The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
2021-02-17 | Conference paper
DOI: 10.1145/3431920.3439296
ISBN: 9781450382182
Source: Self-asserted source
Hongzheng Chen

Entropy-Directed Scheduling for FPGA High-Level Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2020-10 | Journal article
DOI: 10.1109/TCAD.2019.2939325
Contributors: Minghua Shen; Hongzheng Chen; Nong Xiao
Source: check_circle
Crossref

A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
2019-11 | Conference paper
DOI: 10.1109/iccad45719.2019.8942126
ISBN: 9781728123509
Source: Self-asserted source
Hongzheng Chen
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