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Works (9)

Investigation of timing margin in single-flux-quantum 4 bit adders for increasing clock frequency of gate-level-pipelined circuits

Applied Physics Express
2024-05-01 | Journal article
DOI: 10.35848/1882-0786/ad46e5
Contributors: Ikki Nagaoka; Tomoki Nakano; Ryota Kashima; Masamitsu Tanaka; Taro Yamashita; Akira Fujimaki
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Crossref

Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File

IEEE Transactions on Applied Superconductivity
2023 | Journal article
DOI: 10.1109/TASC.2023.3249131
Contributors: Ryota Kashima; Ikki Nagaoka; Tomoki Nakano; Masamitsu Tanaka; Taro Yamashita; Akira Fujimaki
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Crossref

50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic With Frequency-Increased Clock Distribution

IEEE Transactions on Applied Superconductivity
2023-06 | Journal article
DOI: 10.1109/TASC.2023.3250614
Contributors: Ikki Nagaoka; Ryota Kashima; Masamitsu Tanaka; Satoshi Kawakami; Teruo Tanimoto; Taro Yamashita; Koji Inoue; Akira Fujimaki
Source: check_circle
Crossref

A High-Throughput Multiply-Accumulate Unit With Long Feedback Loop Using Low-Voltage Rapid Single-Flux Quantum Circuits

IEEE Transactions on Applied Superconductivity
2023-04 | Journal article
DOI: 10.1109/TASC.2023.3239329
Contributors: Ikki Nagaoka; Ryota Kashima; Koki Ishida; Masamitsu Tanaka; Taro Yamashita; Takatsugu Ono; Koji Inoue; Akira Fujimaki
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Crossref

Demonstration of a 52-GHz Bit-Parallel Multiplier Using Low-Voltage Rapid Single-Flux-Quantum Logic

IEEE Transactions on Applied Superconductivity
2021-08 | Journal article
DOI: 10.1109/TASC.2021.3071996
Contributors: Ikki Nagaoka; Koki Ishida; Masamitsu Tanaka; Kyosuke Sano; Taro Yamashita; Takatsugu Ono; Koji Inoue; Akira Fujimaki
Source: check_circle
Crossref

Investigation of Timing Parameters in Single-Flux-Quantum Circuits Using Low Critical-Current Junctions and Low Bias Voltages

IEEE Transactions on Applied Superconductivity
2021-08 | Journal article
DOI: 10.1109/TASC.2021.3067827
Contributors: Manami Kuniyoshi; Ken Murase; Ikki Nagaoka; Kyosuke Sano; Masamitsu Tanaka; Taro Yamashita; Akira Fujimaki
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Crossref

Superconductor Computing for Neural Networks

IEEE Micro
2021-05-01 | Journal article
DOI: 10.1109/MM.2021.3070488
Contributors: Koki Ishida; Ilkwon Byun; Ikki Nagaoka; Kosuke Fukumitsu; Masamitsu Tanaka; Satoshi Kawakami; Teruo Tanimoto; Takatsugu Ono; Jangwoo Kim; Koji Inoue
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Crossref

Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic

2019 IEEE International Superconductive Electronics Conference (ISEC)
2019-07 | Other
DOI: 10.1109/isec46533.2019.8990905
Contributors: Ikki Nagaoka; Masamitsu Tanaka; Kyosuke Sano; Taro Yamashita; Akira Fujimaki; Koji Inoue
Source: Self-asserted source
Ikki Nagaoka via Crossref Metadata Search

29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic

2019 IEEE International Solid- State Circuits Conference - (ISSCC)
2019-02 | Other
DOI: 10.1109/isscc.2019.8662351
Contributors: Ikki Nagaoka; Masamitsu Tanaka; Koji Inoue; Akira Fujimaki
Source: Self-asserted source
Ikki Nagaoka via Crossref Metadata Search
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