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Works (3)

Modular Pipeline Architecture for Accelerating Join Operation in RDBMS

IEEE Transactions on Circuits and Systems II: Express Briefs
2020-11 | Journal article
DOI: 10.1109/TCSII.2020.2968499
Contributors: Weijie Chen; Weijun Li; Feng Yu
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A Hybrid Pipelined Architecture for High Performance Top-K Sorting on FPGA

IEEE Transactions on Circuits and Systems II: Express Briefs
2020-08 | Journal article
DOI: 10.1109/TCSII.2019.2938892
Contributors: Weijie Chen; Weijun Li; Feng Yu
Source: check_circle
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Resource-Efficient Parallel Tree-Based Join Architecture on FPGA

IEEE Transactions on Circuits and Systems II: Express Briefs
2019-01 | Journal article
DOI: 10.1109/TCSII.2018.2836920
Contributors: Huan Zhang; Bei Zhao; Wei-Jun Li; Zhen-Guo Ma; Feng Yu
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