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A Streaming High-Throughput Linear Sorter System with Contention Buffering

2011-01-11 | Journal article | Principal Investigator
DOI:

10.1155/2011/963539

Contributors: Jorge Ortiz
Source: Self-asserted source
Jorge Ortiz
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A Configurable High-Throughput Linear Sorter System

2010-04 | Conference paper | Author
DOI:

10.1109/IPDPSW.2010.5470730

Contributors: Jorge Ortiz
Source: Self-asserted source
Jorge Ortiz

A Reconfigurable Superscalar Processor Architecture for FPGA-based Designs

2009-07-14 | Conference paper | Author
Part of ISBN:

1601320965

Contributors: Jorge Ortiz
Source: Self-asserted source
Jorge Ortiz

Area Evaluation for Parallel Execution in Reconfigurable Processor Architectures

2009-07-13 | Conference paper | Author
Contributors: Jorge Ortiz
Source: Self-asserted source
Jorge Ortiz

Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link

2004-07 | Journal article | Author
DOI:

10.1109/MM.2004.36

Contributors: Jorge Ortiz
Source: Self-asserted source
Jorge Ortiz