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Scopus Author ID: 57204150069

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Works (10)

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays

Digest of Technical Papers - IEEE International Solid-State Circuits Conference
2021 | Conference paper
DOI: 10.1109/ISSCC42613.2021.9365972
EID:

2-s2.0-85102360530

Part of ISSN: 01936530
Contributors: Santiccioli, A.; Mercandelli, M.; Dartizio, S.M.; Tesolin, F.; Karman, S.; Shehata, A.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A. et al.
Source: Self-asserted source
Mario Mercandelli via Scopus - Elsevier

A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter

Digest of Technical Papers - IEEE International Solid-State Circuits Conference
2021 | Conference paper
DOI: 10.1109/ISSCC42613.2021.9365768
EID:

2-s2.0-85102366969

Part of ISSN: 01936530
Contributors: Mercandelli, M.; Santiccioli, A.; Dartizio, S.M.; Shehata, A.; Tesolin, F.; Karman, S.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A. et al.
Source: Self-asserted source
Mario Mercandelli via Scopus - Elsevier

A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs

IEEE Transactions on Circuits and Systems I: Regular Papers
2021 | Journal article
DOI: 10.1109/TCSI.2021.3072344
EID:

2-s2.0-85104614567

Part of ISSN: 15580806 15498328
Contributors: Avallone, L.; Mercandelli, M.; Santiccioli, A.; Kennedy, M.P.; Levantino, S.; Samori, C.
Source: Self-asserted source
Mario Mercandelli via Scopus - Elsevier

A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter

Digest of Technical Papers - IEEE International Solid-State Circuits Conference
2020 | Conference paper
DOI: 10.1109/ISSCC19947.2020.9063135
EID:

2-s2.0-85083844136

Part of ISSN: 01936530
Contributors: Mercandelli, M.; Santiccioli, A.; Parisi, A.; Bertulessi, L.; Cherniak, D.; Lacaita, A.L.; Samori, C.; Levantino, S.
Source: Self-asserted source
Mario Mercandelli via Scopus - Elsevier

A 250-Mb/s Direct Phase Modulator with -42.4-dB EVM Based on a 14-GHz Digital PLL

IEEE Solid-State Circuits Letters
2020 | Journal article
DOI: 10.1109/LSSC.2020.3006519
EID:

2-s2.0-85087505792

Part of ISSN: 25739603
Contributors: Cherniak, D.; Mercandelli, M.; Bertulessi, L.; Padovan, F.; Grimaldi, L.; Santiccioli, A.; Aichner, M.; Samori, C.; Levantino, S.
Source: Self-asserted source
Mario Mercandelli via Scopus - Elsevier

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking

IEEE Journal of Solid-State Circuits
2020 | Journal article
DOI: 10.1109/JSSC.2020.3019344
EID:

2-s2.0-85097218983

Part of ISSN: 1558173X 00189200
Contributors: Santiccioli, A.; Mercandelli, M.; Bertulessi, L.; Parisi, A.; Cherniak, D.; Lacaita, A.L.; Samori, C.; Levantino, S.
Source: Self-asserted source
Mario Mercandelli via Scopus - Elsevier

A 66fs<inf>rms</inf>Jitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking

Digest of Technical Papers - IEEE International Solid-State Circuits Conference
2020 | Conference paper
DOI: 10.1109/ISSCC19947.2020.9063094
EID:

2-s2.0-85083839044

Part of ISSN: 01936530
Contributors: Santiccioli, A.; Mercandelli, M.; Bertulessi, L.; Parisi, A.; Cherniak, D.; Lacaita, A.L.; Samori, C.; Levantino, S.
Source: Self-asserted source
Mario Mercandelli via Scopus - Elsevier

A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

IEEE Journal of Solid-State Circuits
2019 | Journal article
DOI: 10.1109/JSSC.2019.2941259
EID:

2-s2.0-85074322690

Part of ISSN: 1558173X 00189200
Contributors: Santiccioli, A.; Mercandelli, M.; Lacaita, A.L.; Samori, C.; Levantino, S.
Source: Self-asserted source
Mario Mercandelli via Scopus - Elsevier

A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power

Proceedings of the Custom Integrated Circuits Conference
2019 | Conference paper
DOI: 10.1109/CICC.2019.8780235
EID:

2-s2.0-85070538086

Part of ISSN: 08865930
Contributors: Santiccioli, A.; Mercandelli, M.; Lacaita, A.L.; Samori, C.; Levantino, S.
Source: Self-asserted source
Mario Mercandelli via Scopus - Elsevier

A background calibration technique to control the bandwidth of digital PLLs

IEEE Journal of Solid-State Circuits
2018 | Journal article
DOI: 10.1109/JSSC.2018.2866454
EID:

2-s2.0-85054613652

Part of ISSN: 00189200
Contributors: Mercandelli, M.; Grimaldi, L.; Bertulessi, L.; Samori, C.; Lacaita, A.L.; Levantino, S.
Source: Self-asserted source
Mario Mercandelli via Scopus - Elsevier
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