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Scopus Author ID: 56901096200

Countries

India

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Employment (1)

VNR Vignana Jyothi College of Engineering and Technology: Hyderabad, Telangana, IN

2016-06-01 to 2018-08-08 | Assistant Professor (EIE)
Employment
Source: Self-asserted source
BATCHU SUPRAJA

Education and qualifications (3)

Central Electronics Engineering Research Institute CSIR: Pilani, Rajasthan, IN

2018-08-14 to present | PhD
Education
Source: Self-asserted source
BATCHU SUPRAJA

RGMCET: Nandyal, Andhra Pradesh, IN

2013-08-01 to 2015-11-27 | M.Tech-Embedded Systems (ECE)
Education
Source: Self-asserted source
BATCHU SUPRAJA

RGMCET: Nandyal, Andhra Pradesh, IN

2009-09-23 to 2013-05-01 | B Tech (Electronics and Instrumentation Engineering)
Education
Source: Self-asserted source
BATCHU SUPRAJA

Works (6)

Real-Time Concrete Damage Detection Using Deep Learning for High Rise Structures

IEEE Access
2021 | Journal article
DOI: 10.1109/ACCESS.2021.3102647
Contributors: Prashant Kumar; Supraja Batchu; Narasimha Swamy S.; Solomon Raju Kota
Source: check_circle
Crossref

Power efficient, high frequency and low noise PLL design for wireless receiver applications

Computer, Communication and Electrical Technology - Proceedings of the International Conference on Advancement of Computer Communication and Electrical Technology, ACCET 2016
2017 | Conference paper
EID:

2-s2.0-85034862023
Contributors: Supraja, B.; Ravi, N.; Jayachandra Prasad, T.
Source: Self-asserted source
BATCHU SUPRAJA via Scopus - Elsevier

A hybrid divide—16 frequency divider design for low power phase locked loop design

Advances in Intelligent Systems and Computing
2016 | Book
DOI: 10.1007/978-81-322-2671-0_47
EID:

2-s2.0-84955285242
Contributors: Batchu, S.; Nirlakalla, R.; Talari, J.P.; Surisetty, V.
Source: Self-asserted source
BATCHU SUPRAJA via Scopus - Elsevier

A Phase Frequency Detector and Charge Pump Design to Reduce Current Mismatch of PLL

International Journal of Applied Engineering Research
2015 | Journal article
Source: Self-asserted source
BATCHU SUPRAJA

Analysis of Low Power and High Speed Phase Frequency Detectors for Phase Locked Loop Design

Procedia Computer Science
2015 | Conference paper
DOI: 10.1016/j.procs.2015.07.390
EID:

2-s2.0-84944066359
Contributors: Batchu, S.; Talari, J.P.; Nirlakalla, R.
Source: Self-asserted source
BATCHU SUPRAJA via Scopus - Elsevier

Novel designs for efficient PFD and charge pump designs for phase locked loop

International Journal of Control Theory and Applications
2015 | Journal article
EID:

2-s2.0-84958962630
Contributors: Batchu, S.; Nirlakalla, R.; Talari, J.P.
Source: Self-asserted source
BATCHU SUPRAJA via Scopus - Elsevier
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