José M. Granado-Criado (0000-0002-2356-5587)

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I am, since 2006, an Associate Professor of Computer Architecture in the Department of Computers and Communications Technologies, University of Extremadura, Spain. I received a PhD degree in Computer Science from the University of Extremadura in 2009. I has authored or coauthored more than 50 publications including journal papers (16 JCR-indexed journal papers), book chapters, and peer-reviewed conference proceedings. I has edited 2 special issues of international JCR-indexed journals and an international book, and I has contributed to the organization of several international conferences and workshops. My main research interests are reconfigurable and embedded computing, cryptography, parallel computing, evolutionary computation, and bioinformatics.

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University of Extremadura: Cáceres, Extremadura, ES

2006-05-08 to present | Associate Professor (Technologies of Computers and Communications)

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José M. Granado-Criado

https://orcid.org/0000-0002-2356-5587

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University of Extremadura: Cáceres, Extremadura, ES

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University of Extremadura: Cáceres, Extremadura, ES

University of Extremadura: Cáceres, Extremadura, ES

University of Extremadura: Cáceres, Extremadura, ES

University of Extremadura: Cáceres, Extremadura, ES

Works (50 of 54)

A Simple yet Effective Greedy Evolutionary Strategy for RNA Design

Evolutionary Strategy to Enhance an RNA Design Tool Performance

Solving the RNA inverse folding problem through target structure decomposition and Multiobjective Evolutionary Computation

Fast Montgomery Modular Multiplier Using FPGAs

Multiobjective evolutionary computation for high-order genetic interactions

Parallel evolutionary computation for multiobjective gene interaction analysis

Recommender system implementations for embedded collaborative filtering applications

Multi-Objective Artificial Bee Colony for designing multiple genes encoding the same protein

Parallel Programming in Bioinformatics: Some Interesting Approaches

A Multi-Objective Optimization Procedure for Solving the High-Order Epistasis Detection Problem

Parallel computing in computational biology: a technological point of view

Proceedings of the 6th International Workshop on Parallelism in Bioinformatics

Computación Empotrada De Funciones De Los Sistemas De Recomendación Mediante Fpgas

Hardware coprocessors for high-performance symmetric cryptography

La Autoevaluación y Evaluación por Pares en Distintas Asignaturas: ¿Cómo Afecta a la Mejora de la Docencia?

Optimización Multiobjetivo para el Estudio de Asociaciones Genéticas

Optimización Multiobjetivo Paralela para la Detección de Epistasia de Múltiples Loci

Parallel multi-objective optimization for high-order epistasis detection

Mejorando la Docencia mediante la Aplicación de Sistemas de Autoevaluación y Evaluación por Pares en el Aula

Hardware security platform for multicast communications

A multiobjective swarm intelligence approach based on artificial bee colony for reliable DNA sequence design

Low power consumption security platform for industrial communications using an MPSoC

Biprocesador MicroBlaze para Gestión de Claves de Grupos de Usuarios

Dual MicroBlaze rekeying processor for group key management

A new methodology to implement the AES algorithm using partial and dynamic reconfiguration

Plataforma de cifrado asimétrico utilizando un MPSoC

IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration

Implementación del Algoritmo AES en modo CBC usando un MPSoC

Parallel and runtime reconfigurable implementation of the idea algorithm

Rendimiento de operadores de computación bio-inspirada mediante procesadores paralelos basados en FPGA

Implementación del Algoritmo Criptográfico RC6 usando una Nueva Metodología de Diseño para FPGAs

Implementación Eficiente del Algoritmo AES usando FPGAs, Segmentación y Reconfiguración Dinámica y Parcial

Tele-education of the instruction dynamic scheduling using a web simulator

Using Reconfigurable Computing for the Optimization of Cryptographic Algorithms

A dynamically and partially reconfigurable implementation of the IDEA algorithm using FPGAs and handel-C

Implementación Reconfigurable Paralela y Supersegmentada del Algoritmo Criptográfico IDEA

Tele-education of the instruction dynamic scheduling using a web simulator

A genetic algorithm to design error correcting codes

APRIS: Library and on-line tools to drive parallel adaptive and neural heuristic to improve system identification precision

Implementación mediante Reconfiguración Dinámica y Parcial del Algoritmo Criptográfico IDEA usando Handel-C

Implementing the IDEA cryptographic algorithm in Virtex-E and Virtex-II FPGAs

Reconfigurable computing and parallelism for implementing and accelerating evolutionary algorithms

Teaching Reconfigurable Computing in the new EHEA by means of the multicycle MIPS machine implementation

Using an FPGA implementation of the multicycle MIPS machine to teach reconfigurable computing in the new EHEA

Using FPGAs to implement artificial neural networks

Using FPGAs to Implement Artificial Neural Networks

Design of a wireless network: Research and methodology

Implementación de redes neuronales artificiales utilizando FPGAs

Sunspot Series Prediction Using Adaptive Identification

A Parallel Adaptive Algorithm to Improve Precision of Time Series Identification.