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Works (4)

A Unified Parallel Framework for LUT Mapping and Logic Optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2025-01 | Journal article
DOI: 10.1109/TCAD.2024.3429079
Contributors: Tianji Liu; Yang Sun; Lei Chen; Xing Li; Mingxuan Yuan; Evangeline F. Y. Young
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Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2024-08 | Journal article
DOI: 10.1109/TCAD.2024.3368970
Contributors: Lixin Liu; Tianji Liu; Bentian Jiang; Evangeline F. Y. Young
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Massively Parallel AIG Resubstitution

2024-06-23 | Conference paper
DOI: 10.1145/3649329.3655987
Contributors: Yang Sun; Tianji Liu; Martin D. F. Wong; Evangeline F. Y. Young
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On Advanced Methodologies for Microarchitecture Design Space Exploration

2024-06-12 | Conference paper
DOI: 10.1145/3649476.3658764
Contributors: Tianji Liu; Qijing Wang; Lixin Liu; Fangzhou Wang; Evangeline F.Y. Young
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