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ResearcherID: N-4699-2015

Keywords

cache modeling, opencl, heterogeneous systems, hpc

Countries

Spain

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Employment (1)

Universidade da Coruña: A Coruna, Galicia, ES

2006-10-01 to present | Associate professor (Departamento de Electrónica e Sistemas)
Employment
Source: Self-asserted source
Diego Andrade

Education and qualifications (1)

Universidade da Coruña: A Coruna, Galicia, ES

2007-04-23 to present | Ph.D (Departamento de Electrónica e Sistemas)
Education
Source: Self-asserted source
Diego Andrade

Works (26)

Automatic Generation of Optimized OpenCL Codes Using OCLoptimizer

The Computer Journal
2015 | Journal article
Source: Self-asserted source
Diego Andrade

Developing adaptive multi-device applications with the Heterogeneous Programming Library

The Journal of Supercomputing
2015 | Journal article
Source: Self-asserted source
Diego Andrade

Improving OpenCL Programmability with the Heterogeneous Programming Library

Procedia Computer Science
2015 | Journal article
Source: Self-asserted source
Diego Andrade

A fine-grained thread-aware management policy for shared caches

Concurrency and Computation: Practice and Experience
2014 | Journal article
Source: Self-asserted source
Diego Andrade

Address independent estimation of the boundaries of cache performance

Microprocessors and Microsystems
2014 | Journal article
Source: Self-asserted source
Diego Andrade

Writing self-adaptive codes for heterogeneous systems

Euro-Par 2014 Parallel Processing
2014 | Book chapter
Source: Self-asserted source
Diego Andrade

Accurate prediction of the behavior of multithreaded applications in shared caches

Parallel Computing
2013 | Journal article
Source: Self-asserted source
Diego Andrade

Numerical simulation of pollutant transport in a shallow-water system on the Cell heterogeneous processor

The Journal of Supercomputing
2013 | Journal article
Source: Self-asserted source
Diego Andrade

OCLoptimizer: An iterative optimization tool for OpenCL

Procedia Computer Science
2013 | Journal article
Source: Self-asserted source
Diego Andrade

Static analysis of the worst-case memory performance for irregular codes with indirections

ACM Transactions on Architecture and Code Optimization (TACO)
2012 | Journal article
Source: Self-asserted source
Diego Andrade

Using an Analytical Model of Shared Caches for Selecting the Optimal Parallelization Scheme

Parallel and Distributed Processing with Applications (ISPA), 2012 IEEE 10th International Symposium on
2012 | Conference paper
Source: Self-asserted source
Diego Andrade

An efficient parallel set container for multicore architectures

2011 | Journal article
Source: Self-asserted source
Diego Andrade

Address-independent estimation of the worst-case memory performance

Industrial Informatics, IEEE Transactions on
2010 | Journal article
Source: Self-asserted source
Diego Andrade

Monitorización del trabajo en prácticas usando un sistema decontrol de versiones

Jornadas de Enseñanza Universitaria de la Informática (16es: 2010: Santiago de Compostela)
2010 | Journal article
Source: Self-asserted source
Diego Andrade

Static prediction of worst-case data cache performance in the absence of base address information

Real-Time and Embedded Technology and Applications Symposium, 2009. RTAS 2009. 15th IEEE
2009 | Conference paper
Source: Self-asserted source
Diego Andrade

Task-parallel versus data-parallel library-based programming in multicore systems

Parallel, Distributed and Network-based Processing, 2009 17th Euromicro International Conference on
2009 | Conference paper
Source: Self-asserted source
Diego Andrade

Hierarchically Tiled Array Vs. Intel Thread Building Blocks for Multicore Systems Programming

Programmability Issues for Multi-Core Computers,(MULTIPROG), Goteborg
2008 | Journal article
Source: Self-asserted source
Diego Andrade

Hierarchically Tiled Arrays Vs. Intel Threading Building Blocks for Programming Multicore Systems

Programmability Issues for Multi-Core Computers
2008 | Journal article
Source: Self-asserted source
Diego Andrade

Automated and accurate cache behavior analysis for codes with irregular access patterns

Concurrency and Computation: Practice and Experience
2007 | Journal article
Source: Self-asserted source
Diego Andrade

Cache behavior modelling for codes involving banded matrices

Languages and Compilers for Parallel Computing
2007 | Book chapter
Source: Self-asserted source
Diego Andrade

Precise automatable analytical modeling of the cache behavior of codes with indirections

ACM Transactions on Architecture and Code Optimization (TACO)
2007 | Journal article
Source: Self-asserted source
Diego Andrade

Analytical modeling of codes with arbitrary data-dependent conditional structures

Journal of Systems Architecture
2006 | Journal article
Source: Self-asserted source
Diego Andrade

Optimal tile size selection guided by analytical models

parameters
2005 | Journal article
Source: Self-asserted source
Diego Andrade

Modeling the cache behavior of codes with arbitrary data-dependent conditional structures

Advances in Computer Systems Architecture
2004 | Book chapter
Source: Self-asserted source
Diego Andrade

Cache behavior modeling of codes with data-dependent conditionals

Software and Compilers for Embedded Systems
2003 | Book chapter
Source: Self-asserted source
Diego Andrade

Optimización iterativa de código OpenCL

Journal article
Source: Self-asserted source
Diego Andrade
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