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Scopus Author ID: 12645916300

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Works (40)

A Novel Nanocomposite Polymer Electrolyte for Application in Solid State Lithium Ion Battery

Proceedings of the IEEE Conference on Nanotechnology
2019 | Conference paper
DOI: 10.1109/NANO.2018.8626268
EID:

2-s2.0-85062302470
Contributors: Satyanarayana Reddy, S.S.; Ravindra, J.V.R.; Reddy, N.H.; Polu, A.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Machine learning based power efficient approximate 4:2 compressors for imprecise multipliers

Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019
2019 | Conference paper
DOI: 10.1109/VLSID.2019.00057
EID:

2-s2.0-85066901625
Contributors: Maddisetti, L.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Performance Metrics of Imprecise Multipliers Based on Proximate Compressors for IIR Filters

Proceedings of the International Conference on Microelectronics, ICM
2019 | Conference paper
DOI: 10.1109/ICM.2018.8704044
EID:

2-s2.0-85065707960
Contributors: Lavanya, M.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Performance Metrics of Inexact Multipliers Based on Approximate 5:2 Compressors

Proceedings - International SoC Design Conference 2018, ISOCC 2018
2019 | Conference paper
DOI: 10.1109/ISOCC.2018.8649944
EID:

2-s2.0-85063187464
Contributors: Maddisetti, L.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Power and area optimized FRA-CSLA for high-speed NoC applications

International Journal of Advanced Trends in Computer Science and Engineering
2019 | Journal article
DOI: 10.30534/ijatcse/2019/84832019
EID:

2-s2.0-85068769267
Contributors: Singh, S.; Ravindra, J.V.R.; Rajendra Naik, B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Training neural network as approximate 4:2 compressor applying machine learning algorithms for accuracy comparison

International Journal of Advanced Trends in Computer Science and Engineering
2019 | Journal article
DOI: 10.30534/ijatcse/2019/17822019
EID:

2-s2.0-85068007034
Contributors: Maddisetti, L.; Senapati, R.K.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Low-power near-explicit 5:2 compressor for superior performance multipliers

International Journal of Engineering Research and Technology
2018 | Journal article
EID:

2-s2.0-85055478191
Contributors: Lavanya, M.; Senapati, R.K.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Towards reducing area and power of a multiplier with double precision floating point computations using FPGA accelerators

Journal of Advanced Research in Dynamical and Control Systems
2017 | Journal article
EID:

2-s2.0-85042553647
Contributors: Srikanth, B.; Siva Kumar, M.; Hari Kishore, K.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

A novel and efficient design of golay encoder for ultra deep submicron technologies

2016 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2016
2016 | Conference paper
DOI: 10.1109/ICACCI.2016.7732059
EID:

2-s2.0-85007412581
Contributors: Sheelam, C.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

CALPAN: Countermeasure against Leakage Power Analysis attack by normalized DDPL

Proceedings of IEEE International Conference on Circuit, Power and Computing Technologies, ICCPCT 2016
2016 | Conference paper
DOI: 10.1109/ICCPCT.2016.7530142
EID:

2-s2.0-84992088646
Contributors: Padmini, C.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

JARVIS: Just-Accurate Competent IIR Filter Using Proximate Reversible Adder for Low-Power Applications

Proceedings of International Conference on Computational Intelligence, Modelling and Simulation
2016 | Conference paper
DOI: 10.1109/CIMSim.2015.25
EID:

2-s2.0-84994360861
Contributors: Inapurapu, S.; Ravindra, J.V.R.; Reddy, S.S.S.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

NEON: Near-accurate efficient FIR Filter for ultra low-power applications

International Conference on Applied Electronics
2016 | Conference paper
DOI: 10.1109/AE.2016.7577250
EID:

2-s2.0-84992347182
Contributors: Inapurapu, S.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

PEARL: Performance analysis of ultra low power reversible logic circuits against DPA attacks

International Conference on Electrical, Electronics, and Optimization Techniques, ICEEOT 2016
2016 | Conference paper
DOI: 10.1109/ICEEOT.2016.7755539
EID:

2-s2.0-85006802693
Contributors: Padmini, C.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip

ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
2016 | Conference paper
DOI: 10.1109/ISOCC.2016.7799765
EID:

2-s2.0-85010281722
Contributors: Singh, S.; Ravindra, J.V.R.; Naik, B.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

A novel modulo 2<sup>n</sup> + 1 fused multiply-adder unit for secured VLSI architectures

2014 International Conference on Circuits, Power and Computing Technologies, ICCPCT 2014
2014 | Conference paper
DOI: 10.1109/ICCPCT.2014.7055038
EID:

2-s2.0-84949924123
Contributors: Reddy, N.S.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

A novel polynomial basis multiplier for arbitrary elliptic curves over GF (2<sup>m</sup>)

2014 International Conference for Convergence of Technology, I2CT 2014
2014 | Conference paper
DOI: 10.1109/I2CT.2014.7092022
EID:

2-s2.0-84949928856
Contributors: Mosin, A.; Ravindra, J.V.R.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

A novel analytical model for analysis of delay and crosstalk in non linear RLC interconnects for ultra low power applications

Proceedings - UKSim 15th International Conference on Computer Modelling and Simulation, UKSim 2013
2013 | Conference paper
DOI: 10.1109/UKSim.2013.143
EID:

2-s2.0-84880854646
Contributors: Ravindra, J.V.R.; Yagateela, P.; Prasad, N.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Design of ultra lowpower full adder using modified branch based logic style

Proceedings - UKSim-AMSS 7th European Modelling Symposium on Computer Modelling and Simulation, EMS 2013
2013 | Conference paper
DOI: 10.1109/EMS.2013.116
EID:

2-s2.0-84899527713
Contributors: Ramireddy, G.R.; Ravindra, J.V.R.; Kamatham, H.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Power aware and delay efficient hybrid CMOS full-adder for ultra deep submicron technology

Proceedings - UKSim-AMSS 7th European Modelling Symposium on Computer Modelling and Simulation, EMS 2013
2013 | Conference paper
DOI: 10.1109/EMS.2013.117
EID:

2-s2.0-84899576611
Contributors: Konijeti, N.R.; Ravindra, J.V.R.; Yagateela, P.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Performance modeling of high speed VLSI interconnects

PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
2010 | Conference paper
DOI: 10.1109/PRIMEASIA.2010.5604960
EID:

2-s2.0-78650104616
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Generating reduced order models for high speed VLSI interconnects using balancing-free square root method

12th IEEE Workshop on Signal Propagation on Interconnects, SPI
2008 | Conference paper
DOI: 10.1109/SPI.2008.4558396
EID:

2-s2.0-51849091632
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Generic sub-space algorithm for generating reduced order models of linear time varying VLSI circuits

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
2008 | Conference paper
DOI: 10.1145/1366110.1366138
EID:

2-s2.0-56849106811
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Static superelement technique based macromodeling for high speed nano designs

2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
2008 | Conference paper
DOI: 10.1109/NANO.2008.223
EID:

2-s2.0-55449087418
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

A statistical model for estimating the effect of process variations on delay and slew metrics for VLSI interconnects

Proceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007
2007 | Conference paper
DOI: 10.1109/DSD.2007.4341488
EID:

2-s2.0-47749125754
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Analytical crosstalk model with inductive coupling in VLSI interconnects

Proceedings - 11th IEEE Workshop on Signal Propagation on Interconnects, SPI 2007
2007 | Conference paper
DOI: 10.1109/SPI.2007.4512256
EID:

2-s2.0-77950681984
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Bus coding to minimize redundant bit transitions

IEEE Region 10 Annual International Conference, Proceedings/TENCON
2007 | Conference paper
DOI: 10.1109/TENCON.2007.4429055
EID:

2-s2.0-48649110511
Contributors: Sainarayanan, K.S.; Raghunandan, C.; Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Coupling Aware Energy-Efficient Data Scrambling on Memory-Processor Interfaces

ICIIS 2007 - 2nd International Conference on Industrial and Information Systems 2007, Conference Proceedings
2007 | Conference paper
DOI: 10.1109/ICIINFS.2007.4579214
EID:

2-s2.0-51549084615
Contributors: Sainarayanan, K.S.; Ravindra, J.V.R.; Raghunandan, C.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Delay and energy efficient coding techniques for capacitive interconnects

Journal of Circuits, Systems and Computers
2007 | Journal article
DOI: 10.1142/S0218126607004106
EID:

2-s2.0-44349098718
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Delay and slew analysis of VLSI interconnects using difference model approach

Midwest Symposium on Circuits and Systems
2007 | Conference paper
DOI: 10.1109/MWSCAS.2007.4488792
EID:

2-s2.0-51449121629
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Efficient spatial-temporal coding scheme for minimizing delay in interconnects

IEEE Region 10 Annual International Conference, Proceedings/TENCON
2007 | Conference paper
DOI: 10.1109/TENCON.2006.343715
EID:

2-s2.0-34547561415
Contributors: Sainarayanan, K.S.; Raghunandan, C.; Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Model order reduction for RLC interconnects using response dependent condensation

IEEE Region 10 Annual International Conference, Proceedings/TENCON
2007 | Conference paper
DOI: 10.1109/TENCON.2007.4429084
EID:

2-s2.0-48649085528
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach

Proceedings - SBCCI 2007: 20th Symposium on Integrated Circuits and System Design
2007 | Conference paper
DOI: 10.1145/1284480.1284538
EID:

2-s2.0-37849002822
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Modeling of full-wave high speed on-chip RLC interconnects using frequency shift technique

Proceedings of the Electronic Packaging Technology Conference, EPTC
2007 | Conference paper
DOI: 10.1109/EPTC.2007.4469743
EID:

2-s2.0-50049113017
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Response dependent condensation based macromodeling for linear time varying high speed VLSI interconnects

ISCIT 2007 - 2007 International Symposium on Communications and Information Technologies Proceedings
2007 | Conference paper
DOI: 10.1109/ISCIT.2007.4391982
EID:

2-s2.0-46749152688
Contributors: Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects

Proceedings - IEEE International Symposium on Circuits and Systems
2006 | Conference paper
EID:

2-s2.0-34547246286
Contributors: Sainarayanan, K.S.; Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Coding for minimizing energy in VLSI interconnects

Proceedings of the International Conference on Microelectronics, ICM
2006 | Conference paper
DOI: 10.1109/ICM.2006.373293
EID:

2-s2.0-46749133550
Contributors: Sainarayanan, K.S.; Ravindra, J.V.R.; Nath, K.T.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Energy efficient spatial coding technique for low power VLSI applications

Proceedings - The 6th IEEE International Workshop on System on Chip for Real Time Applications, IWSOC 2006
2006 | Conference paper
DOI: 10.1109/IWSOC.2006.348236
EID:

2-s2.0-44349108289
Contributors: Ravindra, J.V.R.; Chittarvu, N.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Minimizing Simultaneous Switching Noise (SSN) using modified Odd/Even Bus Invert method

Proceedings - Third IEEE International Workshop on Electronic Design, Test and Applications, DELTA 2006
2006 | Conference paper
DOI: 10.1109/DELTA.2006.68
EID:

2-s2.0-33847170492
Contributors: Sainarayanan, K.S.; Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

A novel deep submicron low power bus coding technique

Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005
2005 | Conference paper
EID:

2-s2.0-33244492425
Contributors: Sainarayanan, K.S.; Ravindra, J.V.R.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

An efficient power reduction technique for low power data I/O for military applications

AIAA/IEEE Digital Avionics Systems Conference - Proceedings
2005 | Conference paper
DOI: 10.1109/DASC.2005.1563457
EID:

2-s2.0-33746265053
Contributors: Ravindra, J.V.R.; Sainarayanan, K.S.; Srinivas, M.B.
Source: Self-asserted source
Ravindra JVR via Scopus - Elsevier

Peer review (3 reviews for 1 publication/grant)

Review activity for Journal of institution of engineers (India) series B. (3)
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