Personal information

Biography

I received my Bachelor’s Degree in Electronic Engineering from Polytechnic University of Turin in 2016 and my joint Master's Degree in Micro and Nanotechnologies for Integrated Systems from École polytechnique fédérale de Lausanne (EPFL), Grenoble Institute of Technology and Polytechnic University of Turin in 2018. I am currently pursuing the PhD degree in the Efficient Circuits and IoT Systems Group lead by Prof. Taekwang Jang in ETH Zürich.

My research interests include fully integrated Power Management IC design for next generation computing platforms and Energy Harvesting circuits for ultra-​low power sensor nodes.

Activities

Employment (3)

ETH Zurich: Zurich, CH

2019-01-15 to present | PhD Student (D-ITET IIS)
Employment
Source: Self-asserted source
Alessandro Novello

University of California, Los Angeles: Los Angeles, California, US

2018-02-01 to 2018-08-31 | Visiting Researcher (UCLA Bioengineering)
Employment
Source: Self-asserted source
Alessandro Novello

École Polytechnique Fédérale de Lausanne: Lausanne, Vaud, CH

2017-06-01 to 2017-08-31 | Visiting Researcher (Laboratory of Life Sciences Electronics)
Employment
Source: Self-asserted source
Alessandro Novello

Education and qualifications (2)

EPFL, INP Grenoble, Politecnico di Torino: Lausanne, Grenoble, Torino, CH

2016-09 to 2018-09 | MSc., Micro and Nanotechnologies for Integrated Systems
Education
Source: Self-asserted source
Alessandro Novello

Politecnico di Torino: Torino, Piemonte, IT

2013-09 to 2016-09 | BSc., Electronic Engineering (DET Department of Electronics and Telecommunications)
Education
Source: Self-asserted source
Alessandro Novello

Works (10)

A 1.5-GHz Fully Integrated DC–DC Converter Based on Electromagnetically Coupled Class-D LC Oscillators and Resonant LC Flying Impedance Achieving 4.1-W/mm2 Peak Power Density and 77% Peak Efficiency

IEEE Solid-State Circuits Letters
2024 | Journal article
Contributors: Alessandro Novello; Gabriele Atzeni; Tim Keller; Taekwang Jang
Source: check_circle
Crossref

Design Challenges of Fully Integrated DC–DC Converters for Modern Power Delivery Architectures

IEEE Solid-State Circuits Letters
2024 | Journal article
Contributors: Suyang Song; Alessandro Novello; Taekwang Jang
Source: check_circle
Crossref

A 1.01 NEF Low-Noise Amplifier Using Complementary Parametric Amplification

IEEE Transactions on Circuits and Systems I: Regular Papers
2021 | Journal article
Part of ISSN: 1549-8328
Part of ISSN: 1558-0806
Source: Self-asserted source
Alessandro Novello

A 2.3-GHz Fully Integrated DC–DC Converter Based on Electromagnetically Coupled Class-D LC Oscillators Achieving 78.1% Efficiency in 22-nm FDSOI CMOS

IEEE Solid-State Circuits Letters
2021 | Journal article
Part of ISSN: 2573-9603
Source: Self-asserted source
Alessandro Novello
grade
Preferred source (of 2)‎

A 1.25-GHz Fully Integrated DC–DC Converter Using Electromagnetically Coupled Class-D LC Oscillators

IEEE Journal of Solid-State Circuits
2021-12 | Journal article
Part of ISSN: 0018-9200
Part of ISSN: 1558-173X
Source: Self-asserted source
Alessandro Novello
grade
Preferred source (of 2)‎

A 2.3GHz Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators achieving 78.1% Efficiency in 22nm FDSOI CMOS

2021 Symposium on VLSI Circuits
2021-06-13 | Conference paper
Source: Self-asserted source
Alessandro Novello

17.3 A 1.25GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators

2021 IEEE International Solid- State Circuits Conference (ISSCC)
2021-02-13 | Conference paper
Source: Self-asserted source
Alessandro Novello

A 0.45/0.2-NEF/PEF 12-nV/√Hz Highly Configurable Discrete-Time Low-Noise Amplifier

IEEE Solid-State Circuits Letters
2020 | Journal article
EID:

2-s2.0-85096036735

Part of ISSN: 25739603
Contributors: Atzeni, G.; Novello, A.; Cristiano, G.; Liao, J.; Jang, T.
Source: Self-asserted source
Alessandro Novello via Scopus - Elsevier

A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM-Controlled Frequency-Locked Loops

IEEE Symposium on VLSI Circuits, Digest of Technical Papers
2020 | Conference paper
EID:

2-s2.0-85090228383

Contributors: Cristiano, G.; Liao, J.; Novello, A.; Atzeni, G.; Jang, T.
Source: Self-asserted source
Alessandro Novello via Scopus - Elsevier

An Energy-Efficient Low-Noise Complementary Parametric Amplifier Achieving 0.89 NEF

Midwest Symposium on Circuits and Systems
2020 | Conference paper
EID:

2-s2.0-85090585905

Part of ISSN: 15483746
Contributors: Atzeni, G.; Guichemerre, J.; Novello, A.; Jang, T.
Source: Self-asserted source
Alessandro Novello via Scopus - Elsevier