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Employment (2)

Universidad de Zaragoza: Zaragoza, Aragón, ES

2021-04-08 to present | Associate Professor (Department of Computer Science and Systems Engineering)
Employment
Source: Self-asserted source
Alejandro Valero

Universidad de Zaragoza: Zaragoza, Aragón, ES

2016-09-16 to 2021-04-07 | Assistant Professor (Department of Computer Science and Systems Engineering)
Employment
Source: Self-asserted source
Alejandro Valero

Education and qualifications (3)

Universitat Politècnica de València: Valencia, Valenciana, ES

2010-09-01 to 2013-09-23 | PhD in Computer Engineering (Department of Computer Engineering)
Education
Source: Self-asserted source
Alejandro Valero

Universitat Politècnica de València: Valencia, Valenciana, ES

2009-09-15 to 2011-07-08 | MS in Computer Engineering (Department of Computer Engineering)
Education
Source: Self-asserted source
Alejandro Valero

Universitat Politècnica de València: Valencia, Valenciana, ES

2003-09-15 to 2009-05-06 | BS in Computer Engineering (Department of Computer Engineering)
Education
Source: Self-asserted source
Alejandro Valero

Works (26)

Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators

Journal of Systems Architecture
2024-12 | Journal article
Contributors: Yamilka Toca-Díaz; Rubén Gran Tejero; Alejandro Valero
Source: check_circle
Crossref

Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage

Microprocessors and Microsystems
2024-04 | Journal article
Contributors: Yamilka Toca-Díaz; Reynier Hernández Palacios; Rubén Gran Tejero; Alejandro Valero
Source: check_circle
Crossref

Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators

Journal of Systems Architecture
2022-07 | Journal article
Contributors: Nicolás Landeros Muñoz; Alejandro Valero; Rubén Gran Tejero; Davide Zoni
Source: check_circle
Crossref

A learning experience toward the understanding of abstraction-level interactions in parallel applications

Journal of Parallel and Distributed Computing
2021-10 | Journal article
Contributors: Alejandro Valero; Rubén Gran-Tejero; Darío Suárez-Gracia; Emanuel A. Georgescu; Joaquín Ezpeleta; Pedro Álvarez; Adolfo Muñoz; Luis M. Ramos; Pablo Ibáñez
Source: check_circle
Crossref

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files

IEEE Access
2020 | Journal article
Contributors: Alejandro Valero; Dario Suarez-Gracia; Ruben Gran-Tejero
Source: check_circle
Crossref
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Preferred source (of 3)‎

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer

Proceedings of the Workshop on Computer Architecture Education - WCAE'19
2019 | Other
Contributors: Alejandro Valero; Eduardo Montijano; Javier Resano; María Villarroya-Gaudó; Jesús Alastruey-Benedé; Enrique Torres; Pedro Álvarez; Pablo Ibáñez; Víctor Viñals; Darío Suárez Gracia et al.
Source: Self-asserted source
Alejandro Valero via Crossref Metadata Search
grade
Preferred source (of 4)‎

Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance

IEEE Transactions on Computers
2019-10-01 | Journal article
Contributors: Francisco Candel; Alejandro Valero; Salvador Petit; Julio Sahuquillo
Source: check_circle
Crossref
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An Aging-Aware GPU Register File Design Based on Data Redundancy

IEEE Transactions on Computers
2019-01-01 | Journal article
Contributors: Alejandro Valero; Francisco Candel; Dario Suarez-Gracia; Salvador Petit; Julio Sahuquillo
Source: check_circle
Crossref
grade
Preferred source (of 3)‎

Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache

Euro-Par 2018: Parallel Processing
2018 | Other
Part of ISBN: 9783319969824
Part of ISSN: 0302-9743
Contributors: Francisco Candel; Salvador Petit; Alejandro Valero; Julio Sahuquillo
Source: Self-asserted source
Alejandro Valero via Crossref Metadata Search
grade
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Exploiting Data Compression to Mitigate Aging in GPU Register Files

Proceedings - 29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017
2017 | Conference paper
EID:

2-s2.0-85041218229

Contributors: Candel, F.; Valero, A.; Petit, S.; Suárez-Gracia, D.; Sahuquillo, J.
Source: Self-asserted source
Alejandro Valero via Scopus - Elsevier
grade
Preferred source (of 2)‎

On Microarchitectural Mechanisms for Cache Wearout Reduction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2017-03 | Journal article
Contributors: Alejandro Valero; Negar Miralaei; Salvador Petit; Julio Sahuquillo; Timothy M. Jones
Source: check_circle
Crossref
grade
Preferred source (of 3)‎

Enhancing the L1 Data Cache Design to Mitigate HCI

IEEE COMPUTER ARCHITECTURE LETTERS
2016 | Journal article
Source: check_circle
Universidad de Zaragoza
grade
Preferred source (of 3)‎

A Reuse-Based Refresh Policy for Energy-Aware eDRAM Caches

MICROPROCESSORS AND MICROSYSTEMS
2015 | Journal article
Source: check_circle
Universidad de Zaragoza
grade
Preferred source (of 3)‎

Design of Hybrid Second-Level Caches

IEEE TRANSACTIONS ON COMPUTERS
2015 | Journal article
Source: check_circle
Universidad de Zaragoza
grade
Preferred source (of 3)‎

Analyzing the optimal voltage/frequency pair in fault-tolerant caches

Proceedings - 16th IEEE International Conference on High Performance Computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International Symposium on Cyberspace Safety and Security, CSS 2014
2014 | Conference paper
EID:

2-s2.0-84983108498

Contributors: Lorente, V.; Valero, A.; Petit, S.; Foglia, P.; Sahuquillo, J.
Source: Self-asserted source
Alejandro Valero via Scopus - Elsevier
grade
Preferred source (of 2)‎

Enhancing performance and energy consumption of HER caches by adding associativity

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2014 | Book
EID:

2-s2.0-84958553701

Contributors: Lorente, V.; Valero, A.; Canal, R.
Source: Self-asserted source
Alejandro Valero via Scopus - Elsevier
grade
Preferred source (of 3)‎

Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes

Proceedings -Design, Automation and Test in Europe, DATE
2013 | Conference paper
EID:

2-s2.0-84885663644

Contributors: Lorente, V.; Valero, A.; Sahuquillo, J.; Petit, S.; Canal, R.; López, P.; Duato, J.
Source: Self-asserted source
Alejandro Valero via Scopus - Elsevier

Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches

Proceedings of the International Conference on Supercomputing
2013 | Conference paper
EID:

2-s2.0-84879831521

Contributors: Valero, A.; Sahuquillo, J.; Petit, S.; Duato, J.
Source: Self-asserted source
Alejandro Valero via Scopus - Elsevier
grade
Preferred source (of 2)‎

Analyzing the optimal ratio of SRAM banks in hybrid caches

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
2012 | Conference paper
EID:

2-s2.0-84872069771

Contributors: Valero, A.; Sahuquillo, J.; Petit, S.; López, P.; Duato, J.
Source: Self-asserted source
Alejandro Valero via Scopus - Elsevier
grade
Preferred source (of 2)‎

Combining Recency of Information with Selective Random and a Victim Cache in Last-Level Caches

ACM Transactions on Architecture and Code Optimization
2012 | Journal article
Source: check_circle
Universidad de Zaragoza
grade
Preferred source (of 3)‎

Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches

IEEE TRANSACTIONS ON COMPUTERS
2012 | Journal article
Source: check_circle
Universidad de Zaragoza
grade
Preferred source (of 3)‎

Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
2012 | Journal article
Source: check_circle
Universidad de Zaragoza
grade
Preferred source (of 3)‎

Improving Last-Level Cache performance by exploiting the concept of MRU-Tour

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
2011 | Conference paper
EID:

2-s2.0-84856522622

Contributors: Valero, A.; Sahuquillo, J.; Petit, S.; López, P.; Duato, J.
Source: Self-asserted source
Alejandro Valero via Scopus - Elsevier
grade
Preferred source (of 2)‎

MRU-tour-based replacement algorithms for last-level caches

Proceedings - Symposium on Computer Architecture and High Performance Computing
2011 | Conference paper
EID:

2-s2.0-84855594376

Contributors: Valero, A.; Sahuquillo, J.; Petit, S.; López, P.; Duato, J.
Source: Self-asserted source
Alejandro Valero via Scopus - Elsevier
grade
Preferred source (of 2)‎

An hybrid eDRAM/SRAM macrocell to implement first-level data caches

Proceedings of the Annual International Symposium on Microarchitecture, MICRO
2009 | Conference paper
EID:

2-s2.0-76749128041

Contributors: Valero, A.; Sahuquillo, J.; Petit, S.; Lorente, V.; Canal, R.; López, P.; Duato, J.
Source: Self-asserted source
Alejandro Valero via Scopus - Elsevier
grade
Preferred source (of 2)‎

Hybrid caches: design and data management

Dissertation or Thesis
Part of ISBN: 9788490481370
Contributors: Alejandro Valero Bresó
Source: Self-asserted source
Alejandro Valero via Crossref Metadata Search
grade
Preferred source (of 2)‎

Peer review (4 reviews for 3 publications/grants)

Review activity for IEEE access : (2)
Review activity for IEEE transactions on very large scale integration (VLSI) systems. (1)
Review activity for Journal of ambient intelligence & humanized computing (1)