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Works (32)

Automated handwriting analysis and personality attribute discernment using self-attention multi-resolution analysis

Indonesian Journal of Electrical Engineering and Computer Science
2025-04-01 | Journal article
Contributors: Yashomati R. Dhumal; Arundhati A. Shinde; Roshnadevi Jaising Sapkal; Satish Bhairannawar
Source: check_circle
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Efficient reconfigurable architecture to extract image features for face recognition using local binary pattern

Soft Computing
2025-02 | Journal article
Contributors: Sumangala Bhavikatti; Satish Bhairannawar
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An efficient controller-based architecture for AES algorithm using FPGA

Indonesian Journal of Electrical Engineering and Computer Science
2024 | Journal article
EID:

2-s2.0-85192055887

Part of ISSN: 25024760 25024752
Contributors: Nadaf, R.; Bhairannawar, S.S.
Source: Self-asserted source
satish via Scopus - Elsevier
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Chilli Leaf Disease Identification Using Histrogram Equalisation Technique

5th International Conference on Circuits, Control, Communication and Computing, I4C 2024
2024 | Conference paper
EID:

2-s2.0-85211931856

Part of ISBN: 9798331528539
Contributors: Bhairannawar, S.; Hosur, K.; Bilagi, S.; Patil, S.P.
Source: Self-asserted source
satish via Scopus - Elsevier

9/7 LIFT Reconfigurable Architecture Implementation for Image Authentication

International Journal on Recent and Innovation Trends in Computing and Communication
2023 | Journal article
EID:

2-s2.0-85172790851

Part of ISSN: 23218169
Contributors: Marakumbi, P.; Bhairannawar, S.
Source: Self-asserted source
satish via Scopus - Elsevier

Chili Disease Detection and Classification using Various Machine Learning Techniques

International Conference on Applied Intelligence and Sustainable Computing, ICAISC 2023
2023 | Conference paper
EID:

2-s2.0-85168764991

Part of ISBN: 9798350323795
Contributors: Sambrani, Y.; Rajashekarappa; Bhairannawar, S.
Source: Self-asserted source
satish via Scopus - Elsevier

EEG Classification Using Modified KNN Algorithm

International Conference on Applied Intelligence and Sustainable Computing, ICAISC 2023
2023 | Conference paper
EID:

2-s2.0-85168775616

Part of ISBN: 9798350323795
Contributors: Thejaswini, B.M.; Satheesha, T.Y.; Bhairannawar, S.
Source: Self-asserted source
satish via Scopus - Elsevier

Efficient FPGA architecture to implement non-separable fast Fourier transform for image and video applications

International Journal of Electronics
2023 | Journal article
EID:

2-s2.0-85129594628

Part of ISSN: 13623060 00207217
Contributors: Sarkar, S.; Bhairannawar, S.S.
Source: Self-asserted source
satish via Scopus - Elsevier
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Efficient reconfigurable architecture to enhance medical image security

Indonesian Journal of Electrical Engineering and Computer Science
2023 | Journal article
EID:

2-s2.0-85152093539

Part of ISSN: 25024760 25024752
Contributors: Marakumbi, P.; Bhairannawar, S.
Source: Self-asserted source
satish via Scopus - Elsevier
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Efficient Reconfigurable Architecture to Extract Image Features using Local Binary Pattern for Face recognition

Research Square
2023 | Other
EID:

2-s2.0-85167554301

Contributors: Bhavikatti, S.; Bhairannawar, S.
Source: Self-asserted source
satish via Scopus - Elsevier
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Organising Chair's Message

International Conference on Applied Intelligence and Sustainable Computing, ICAISC 2023
2023 | Conference paper
EID:

2-s2.0-85169149641

Contributors: Bhairannawar, S.
Source: Self-asserted source
satish via Scopus - Elsevier

Plant Leaf Disease Classification Using Modified SVM with Post Processing Techniques

International Conference on Applied Intelligence and Sustainable Computing, ICAISC 2023
2023 | Conference paper
EID:

2-s2.0-85168758418

Part of ISBN: 9798350323795
Contributors: Thyagaraj, R.; Satheesha, T.Y.; Bhairannawar, S.
Source: Self-asserted source
satish via Scopus - Elsevier

Efficient de-noising technique for electroencephalogram signal processing

IAES International Journal of Artificial Intelligence
2022 | Journal article
EID:

2-s2.0-85129224151

Part of ISSN: 22528938 20894872
Contributors: Dalal, V.; Bhairannawar, S.
Source: Self-asserted source
satish via Scopus - Elsevier

Efficient electro encephelogram classification system using support vector machine classifier and adaptive learning technique

Indonesian Journal of Electrical Engineering and Computer Science
2022 | Journal article
EID:

2-s2.0-85122076870

Part of ISSN: 25024760 25024752
Contributors: Dalal, V.B.; Bhairannawar, S.S.
Source: Self-asserted source
satish via Scopus - Elsevier

Computer game-based telerehabilitation platform targeting manual dexterity: Exercise is fun. “you are kidding—right?”

Sensors
2021 | Journal article
EID:

2-s2.0-85113566997

Part of ISSN: 14248220
Contributors: Parmar, S.T.; Kanitkar, A.; Sepehri, N.; Bhairannawar, S.; Szturm, T.
Source: Self-asserted source
satish via Scopus - Elsevier

Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications

Multidimensional Systems and Signal Processing
2021 | Journal article
EID:

2-s2.0-85099918565

Part of ISSN: 15730824 09236082
Contributors: Sarkar, S.; Bhairannawar, S.S.
Source: Self-asserted source
satish via Scopus - Elsevier

FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing

IET Circuits, Devices and Systems
2021 | Journal article
EID:

2-s2.0-85105225733

Part of ISSN: 1751858X
Contributors: Sarkar, S.; Bhairannawar, S.S.; Raja, K.B.
Source: Self-asserted source
satish via Scopus - Elsevier

FPGA Implementation of Optimized Karhunen–Loeve Transform for Image Processing Applications

Journal of Real-Time Image Processing
2020 | Journal article
EID:

2-s2.0-85046457742

Part of ISBN:

18618219 18618200

Contributors: Bhairannawar, S.S.; Sarkar, S.; Raja, K.B.
Source: Self-asserted source
satish via Scopus - Elsevier

A reconfigurable architecture for object detection using adaptive threshold

International Journal of Advanced Computer Research
2018 | Journal article
EID:

2-s2.0-85054349175

Part of ISBN:

22777970 22497277

Contributors: Gangannavar, S.M.; Navalgund, S.S.; Bhairannawar, S.S.
Source: Self-asserted source
satish via Scopus - Elsevier

An efficient FPGA based NoC architecture for data communication

International Journal of Advanced Computer Research
2018 | Journal article
EID:

2-s2.0-85058083406

Part of ISBN:

22777970 22497277

Contributors: Jamagoud, V.; Bhairannawar, S.S.
Source: Self-asserted source
satish via Scopus - Elsevier

Efficient medical image enhancement technique using transform HSV space and adaptive histogram equalization

Soft Computing Based Medical Image Analysis
2018 | Book chapter
EID:

2-s2.0-85052633077

Contributors: Bhairannawar, S.S.
Source: Self-asserted source
satish via Scopus - Elsevier

Implementation of Fingerprint Based Biometric System Using Optimized 5/3 DWT Architecture and Modified CORDIC Based FFT

Circuits, Systems, and Signal Processing
2018 | Journal article
EID:

2-s2.0-85040091017

Part of ISBN:

15315878 0278081X

Contributors: Bhairannawar, S.S.; Sarkar, S.; Raja, K.B.; Venugopal, K.R.
Source: Self-asserted source
satish via Scopus - Elsevier

Color image enhancement using Laplacian filter and contrast limited adaptive histogram equalization

2017 Innovations in Power and Advanced Computing Technologies, i-PACT 2017
2017 | Conference paper
EID:

2-s2.0-85045728238

Contributors: Bhairannawar, S.; Patil, A.; Janmane, A.; Huilgol, M.
Source: Self-asserted source
satish via Scopus - Elsevier

Image compression using self organizing map and discrete wavelet transform with error correction

International Journal of Applied Engineering Research
2017 | Journal article
EID:

2-s2.0-85020912245

Part of ISBN:

09739769 09734562

Contributors: Raju, S.; Bhairannawar, S.S.
Source: Self-asserted source
satish via Scopus - Elsevier

An Adaptive Threshold based FPGA Implementation for Object and Face detection

Proceedings of 2015 3rd International Conference on Image Information Processing, ICIIP 2015
2016 | Conference paper
EID:

2-s2.0-84969628947

Contributors: Kumar, S.H.C.; Sarkar, S.; Bhairannawar, S.S.; Raja, K.B.; Venugopal, K.R.
Source: Self-asserted source
satish via Scopus - Elsevier

Design and Implementation of High Speed Background Subtraction Algorithm for Moving Object Detection

Procedia Computer Science
2016 | Conference paper
EID:

2-s2.0-84985905201

Part of ISBN:

18770509

Contributors: Hanchinamani, S.R.; Sarkar, S.; Bhairannawar, S.S.
Source: Self-asserted source
satish via Scopus - Elsevier

FPGA implementation of face recognition system using efficient 5/3 2D-lifting scheme

2016 International Conference on VLSI Systems, Architectures, Technology and Applications, VLSI-SATA 2016
2016 | Conference paper
EID:

2-s2.0-84995487767

Contributors: Bhairannawar, S.S.; Kumar, R.; Mirji, V.; Sindhu, P.S.
Source: Self-asserted source
satish via Scopus - Elsevier

An Efficient Reconfigurable Architecture for Fingerprint Recognition

VLSI Design
2016-07-28 | Journal article
Contributors: Satish S. Bhairannawar; K. B. Raja; K. R. Venugopal
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An efficient VLSI architecture for fingerprint recognition using O2D-DWT architecture and modified CORDIC-FFT

2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems, SPICES 2015
2015 | Conference paper
EID:

2-s2.0-84937124327

Contributors: Bhairannawar, S.S.; Sarkar, S.; Raja, K.B.; Venugopal, K.R.
Source: Self-asserted source
satish via Scopus - Elsevier

Notice of Removal: FPGA Implementation of Fingerprint Recognition System using Adaptive Threshold Technique

International Conference on Electrical, Electronics, Signals, Communication and Optimization, EESCO 2015
2015 | Conference paper
EID:

2-s2.0-84958012845

Contributors: Bhairannawar, S.S.; Anand, R.; Raja, K.B.; Venugopal, K.R.
Source: Self-asserted source
satish via Scopus - Elsevier

FPGA implementation of high speed Vedic multiplier using CSLA for parallel FIR architecture

Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS
2014 | Conference paper
EID:

2-s2.0-84908288844

Part of ISBN:

15416275

Contributors: Naaz, S.A.; Pradeep, M.N.; Bhairannawar, S.; Halvi, S.
Source: Self-asserted source
satish via Scopus - Elsevier

FPGA based Recursive Error Free Mitchell Log Multiplier for image Filters

2012 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2012
2012 | Conference paper
EID:

2-s2.0-84877991561

Contributors: Bhairannawar, S.S.; Rathan, R.; Raja, K.B.; Venugopal, K.R.; Patnaik, L.M.
Source: Self-asserted source
satish via Scopus - Elsevier