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Works (5)

A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias

IEEE Transactions on Circuits and Systems I: Regular Papers
2023 | Journal article
Contributors: Adrian Kneip; David Bol
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IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization

IEEE Journal of Solid-State Circuits
2023-07 | Journal article
Contributors: Adrian Kneip; Martin Lefebvre; Julien Verecken; David Bol
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A 1-to-4b 16.8-POPS/W 473-TOPS/mm² 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
2022-09-19 | Conference paper
Contributors: Adrian Kneip; Martin Lefebvre; Julien Verecken; David Bol
Source: Self-asserted source
Adrian Kneip

SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management

2021 Symposium on VLSI Circuits
2021-06-13 | Conference paper
Source: Self-asserted source
Adrian Kneip

Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing

IEEE Transactions on Circuits and Systems I: Regular Papers
2021-05 | Journal article
Contributors: Adrian Kneip; David Bol
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Crossref