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Scopus Author ID: 57207927212

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Education and qualifications (3)

Jamia Millia Islamia: New Delhi, Delhi, IN

2015-10-01 to 2021-12-27 | Ph. D. (Electronics & Communication Engineering)
Education
Source: Self-asserted source
Mohd Rizwan Uddin Shaikh

Delhi Technological University: Delhi, Delhi, IN

2012-09-01 to 2015-08-17 | M. Tech (VLSI Design & Embedded System) (Electronics & Communication Engineering )
Education
Source: Self-asserted source
Mohd Rizwan Uddin Shaikh

Rajiv Gandhi Proudyogiki Vishwavidyalaya: Bhopal, Madhya Pradesh, IN

2008-09-11 to 2012-06-08 | B. E. (Electronics & Communication Engineering)
Education
Source: Self-asserted source
Mohd Rizwan Uddin Shaikh

Works (7)

Optimization of DE-QG TFET using novel CIP and DCT techniques

Microelectronics Journal
2024-02 | Journal article
DOI: 10.1016/j.mejo.2024.106097
Part of ISSN: 0026-2692
Contributors: MANIVANNAN T S; K.R. Pasupathy; Mohd Rizwan Uddin Shaikh; G. Lakshminarayanan
Source: Self-asserted source
Mohd Rizwan Uddin Shaikh

Leakage mitigation in NW FET using negative Schottky junction drain and its process variation analysis

Journal of Computational Electronics
2021-12 | Journal article
DOI: 10.1007/s10825-021-01813-5
Contributors: Mohd Rizwan Uddin Shaikh; Sajad A. Loan; Abdullah G. Alharbi
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Analytical Modelling and Benchmarking of Fully Depleted Buried Metal Layer Junctionless Transistor

IEEE International Conference on Semiconductor Electronics (ICSE)
2020 | Conference paper
WOSUID: WOS:000784182200005
Contributors: Shaikh, Mohd Rizwan Uddin; Loan, Sajad A.
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Analytical Modelling and Benchmarking of Fully Depleted Buried Metal Layer Junctionless Transistor

2020 IEEE International Conference on Semiconductor Electronics (ICSE)
2020 | Conference paper
DOI: 10.1109/ICSE49846.2020.9166863
Source: Self-asserted source
Mohd Rizwan Uddin Shaikh
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Electrostatically doped drain engineered DG-TFET: Proposal and analysis

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
2020 | Journal article
DOI: https://doi.org/10.1002/jnm.2769
Source: Self-asserted source
Mohd Rizwan Uddin Shaikh
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Simulation Study of a Split-Channel Quad-Gate Tunnel Field-Effect Transistor

2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)
2019 | Conference paper
DOI: 10.1109/SPIN.2019.8711675
Source: Self-asserted source
Mohd Rizwan Uddin Shaikh
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Drain-Engineered TFET With Fully Suppressed Ambipolarity for High-Frequency Application

IEEE Transactions on Electron Devices
2019-04 | Journal article
DOI: 10.1109/TED.2019.2896674
Contributors: Mohd Rizwan Uddin Shaikh; Sajad A Loan
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