Personal information

India

Activities

Employment (1)

Indian Institute of Technology BHU: Varanasi, U.P, IN

2019-08-27 to present | Assistant Professor (Electronics Engg.)
Employment
Source: Self-asserted source
SHIVAM VERMA

Education and qualifications (3)

Indian Institute of Technology Roorkee: Roorkee, UTTARAKHAND, IN

2013-01-01 to 2017-01-04 | Ph.D. (ELECTRONICS AND COMMUNICATION ENGINEERING)
Education
Source: Self-asserted source
SHIVAM VERMA

Institute of Technology Banaras Hindu University: Varanasi, Uttar Pradesh, IN

2010-07-07 to 2012-06-15 | M.TECH (ELECTRONICS ENGINEERING)
Education
Source: Self-asserted source
SHIVAM VERMA

SHRI VAISHNAV INSTITUTE OF TECHNOLOGY AND SCIENCE: INDORE, MADHYA PRADESH, IN

2006-08-21 to 2010-06-30 | BACHELOR OF ENGINEERING (ELECTRONICS AND COMMUNICATION ENGINEERING)
Education
Source: Self-asserted source
SHIVAM VERMA

Works (18)

Junctionless accumulation-mode SOI ferroelectric FinFET for synaptic weights

Microelectronics Journal
2024-11 | Journal article
Contributors: Roopesh Singh; Sushant Mittal; Shivam Verma
Source: check_circle
Crossref

Design space exploration and power optimization of STT MRAM using trimmed fin Asymmetric FinFET

Microelectronics Journal
2024-07 | Journal article
Contributors: Ashok Kumar; Jagadish Rajpoot; Shivam Verma
Source: check_circle
Crossref

Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory Applications

IEEE Transactions on Circuits and Systems II: Express Briefs
2023 | Journal article
Contributors: Jagadish Rajpoot; Shivam Verma
Source: check_circle
Crossref

SPICE-Based Compact Model for Voltage-Induced Magnetocapacitance in Magnetic Tunnel Junctions

IEEE Transactions on Magnetics
2023-09 | Journal article
Contributors: Jagadish Rajpoot; Ravneet Paul; Shivam Verma
Source: check_circle
Crossref

FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance Enhancement

IEEE Transactions on Electron Devices
2022-12 | Journal article
Contributors: Roopesh Singh; Shivam Verma; Sushant Mittal
Source: check_circle
Crossref

Non-Volatile Latch Compatible With Static and Dynamic CMOS for Logic in Memory Applications

IEEE Transactions on Magnetics
2022-04 | Journal article
Contributors: Shivam Verma; Ravneet Paul; Mayank Shukla
Source: check_circle
Crossref

Modeling of a Magnetic Tunnel Junction for a Multilevel STT-MRAM Cell

IEEE Transactions on Nanotechnology
2019 | Journal article
Part of ISSN: 1536-125X
Part of ISSN: 1941-0085
Source: Self-asserted source
SHIVAM VERMA
grade
Preferred source (of 2)‎

Optimal Boolean Logic Quantum Circuit Decomposition for Spin-Torque-Based <inline-formula> <tex-math notation="LaTeX">$\boldsymbol{n}$ </tex-math> </inline-formula>-Qubit Architecture

IEEE Transactions on Magnetics
2018-10 | Journal article
Contributors: Anant Kulkarni; Sanjay Prajapati; Shivam Verma; Brajesh Kumar Kaushik
Source: check_circle
Crossref

Next Generation Spin Torque Memories

SpringerBriefs in Applied Sciences and Technology
2017 | Book
Part of ISSN: 2191-530X
Part of ISSN: 2191-5318
Source: Self-asserted source
SHIVAM VERMA

Spintronics-Based Devices to Circuits: Perspectives and challenges.

IEEE Nanotechnology Magazine
2016-12 | Journal article
Part of ISSN: 1932-4510
Source: Self-asserted source
SHIVAM VERMA

Performance Enhancement of STT MRAM Using Asymmetric- Sidewall-Spacer NMOS

IEEE Transactions on Electron Devices
2016-07 | Journal article
Contributors: Shivam Verma; Pankaj Kumar Pal; Sanjay Mahawar; Brajesh Kumar Kaushik
Source: check_circle
Crossref

Highly reliable STT MRAM using fully depleted body and buried 4H-SiC NMOS

Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
2015 | Conference paper
EID:

2-s2.0-84962136088

Contributors: Mahawar, S.; Verma, S.; Pal, P.K.; Kaushik, B.K.
Source: Self-asserted source
SHIVAM VERMA via Scopus - Elsevier

Low power STT MRAM cell with asymmetric drive current vertical GAA select device

ECTI-CON 2015 - 2015 12th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology
2015 | Conference paper
EID:

2-s2.0-84957006336

Contributors: Verma, S.; Mahawar, S.; Kaushik, B.K.
Source: Self-asserted source
SHIVAM VERMA via Scopus - Elsevier

Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon Nanowire Platform

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2015 | Journal article
Source: check_circle
Crossref
grade
Preferred source (of 2)‎

Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-design

Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
2015 | Conference paper
EID:

2-s2.0-84962193131

Contributors: Pal, P.K.; Verma, S.; Kaushik, B.K.; Dasgupta, S.
Source: Self-asserted source
SHIVAM VERMA via Scopus - Elsevier

All Spin Logic: A Micromagnetic Perspective

IEEE Transactions on Magnetics
2015-10 | Journal article
Source: check_circle
Crossref
grade
Preferred source (of 2)‎

Modeling of in-plane magnetic tunnel junction for mixed mode simulations

IEEE Transactions on Magnetics
2014 | Journal article
EID:

2-s2.0-84953240311

Contributors: Verma, S.; Kaundal, S.; Kaushik, B.K.
Source: Self-asserted source
SHIVAM VERMA via Scopus - Elsevier

Novel 4 F<sup>2</sup> Buried-source-line STT MRAM cell with vertical GAA transistor as select device

IEEE Transactions on Nanotechnology
2014 | Journal article
EID:

2-s2.0-84910684365

Contributors: Verma, S.; Kaundal, S.; Kaushik, B.K.
Source: Self-asserted source
SHIVAM VERMA via Scopus - Elsevier

Peer review (6 reviews for 3 publications/grants)

Review activity for Journal of electronic materials. (3)
Review activity for Memories, materials, devices, circuits and systems. (2)
Review activity for Micro and nano systems letters. (1)