Personal information

Other IDs

Scopus Author ID: 57190191586
Scopus Author ID: 57205268683
ResearcherID: G-8090-2019

Keywords

VLSI DESIGN

Countries

India

Activities

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Employment (2)

Oriental College of Technology: Bhopal, Madhya Pradesh, IN

2019-12-31 to present | Professor and Head (Electronics and Communication)
Employment
Source: Self-asserted source
Dr. Sandeep Garg

Radharaman Group of Institutes: Bhopal, Madhya Pradesh, IN

2012-06-01 to 2018-07-02 | Assistant Professor (Electronics and Communication)
Employment
Source: Self-asserted source
Dr. Sandeep Garg

Education and qualifications (3)

Maulana Azad National Institute of Technology: Bhopal, Madhya Pradesh, IN

2014-08-06 to 2019-11-09 | Doctor of Philosophy (Electronics and Communication)
Qualification
Source: Self-asserted source
Dr. Sandeep Garg

Shri Govindram Seksaria Institute of Technology and Science: Indore, Madhya Pradesh, IN

2008-08-18 to 2010-08-12 | Master of Technology (Electronics and Instrumentation)
Education
Source: Self-asserted source
Dr. Sandeep Garg

Institute of Engineering and Technology, Devi Ahilya Vishwavidyalaya: Indore, Madhya Pradesh, IN

1998-07-10 to 2006-06-15 | Bachelor of Engineering (Electronics and Instrumentation)
Education
Source: Self-asserted source
Dr. Sandeep Garg

Works (11)

Analysis of Hybrid Spectrum Sensing in Cognitive Radio Using Hybrid Approaches

Communications - Scientific letters of the University of Zilina
2025-01-02 | Journal article
DOI: 10.26552/com.C.2025.003
Contributors: Haribhau Ashok Shinde; Sandeep Garg
Source: check_circle
Crossref

Impact of Silicon Stacked Transistors on Nano Scale Domino Logic

Silicon
2022-01-06 | Journal article
DOI: 10.1007/s12633-021-01629-9
Part of ISSN: 1876-990X
Part of ISSN: 1876-9918
Source: Self-asserted source
Dr. Sandeep Garg
grade
Preferred source (of 2)‎

A 4:1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET

Circuit World
2021-10-25 | Journal article
DOI: 10.1108/cw-09-2019-0128
Part of ISSN: 0305-6120
Part of ISSN: 0305-6120
Source: Self-asserted source
Dr. Sandeep Garg
grade
Preferred source (of 2)‎

SCDNDTDL: a technique for designing low-power domino circuits in FinFET technology

Journal of Computational Electronics
2020-09-23 | Journal article
DOI: 10.1007/s10825-020-01499-1
Contributors: Sandeep Garg; Tarun K. Gupta
Source: check_circle
Crossref
grade
Preferred source (of 2)‎

A 4:1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology

International Journal of Electronics
2020-04-02 | Journal article
DOI: 10.1080/00207217.2019.1663942
Contributors: Sandeep Garg; Tarun K. Gupta; Amit K. Pandey
Source: check_circle
Crossref

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

International Journal of Circuit Theory and Applications
2020-01 | Journal article
DOI: 10.1002/cta.2714
Contributors: Sandeep Garg; Tarun K. Gupta; Amit K. Pandey
Source: check_circle
Crossref
grade
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FDSTDL: Low‐power technique for FinFET domino circuits

International Journal of Circuit Theory and Applications
2019-06 | Journal article
DOI: 10.1002/cta.2627
Contributors: Sandeep Garg; Tarun K. Gupta
Source: check_circle
Crossref
grade
Preferred source (of 2)‎

Very Low Power Domino Logic Circuits Using Carbon Nanotube Field Effect Transistor Technology

Journal of Nanoelectronics and Optoelectronics
2019-01-01 | Journal article
DOI: 10.1166/jno.2019.2419
Part of ISSN: 1555-130X
Contributors: Sandeep Garg; Tarun K. Gupta
Source: Self-asserted source
Dr. Sandeep Garg via Crossref Metadata Search

Low power domino logic circuits in deep-submicron technology using CMOS

Engineering Science and Technology, an International Journal
2018 | Journal article
DOI: 10.1016/J.JESTCH.2018.06.013
WOSUID: WOS:000440526200006
Contributors: Garg, Sandeep; Gupta, Tarun Kumar
Source: check_circle
Web of Science Researcher Profile Sync

A Low leakage domino logic circuit for Wide Fan-in gates using CNTFET

IET Circuits, Devices & Systems
2018-08 | Journal article
DOI: 10.1049/iet-cds.2018.5135
Part of ISSN: 1751-858X
Contributors: Sandeep Garg; TARUN GUPTA
Source: Self-asserted source
Dr. Sandeep Garg via Crossref Metadata Search
grade
Preferred source (of 4)‎

Techniques for designing analog baseband filter: A review

Smart Innovation, Systems and Technologies
2016 | Book
DOI: 10.1007/978-3-319-30933-0_19
EID:

2-s2.0-84978288750
Contributors: Garg, S.; Gupta, T.K.
Source: Self-asserted source
Dr. Sandeep Garg via Scopus - Elsevier
grade
Preferred source (of 2)‎
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