Personal information

Austria

Activities

Employment (3)

Graz University of Technology: Graz, AT

2019-09-01 to present | Research and Teaching Associate (Institute of Technical Informatics)
Employment
Source: Self-asserted source
Tobias Scheipel

AVL List GmbH: Graz, AT

2017-12 to 2020-11 | Project Manager R&D (PTE)
Employment
Source: Self-asserted source
Tobias Scheipel

Graz University of Technology: Graz, AT

2017-12 to 2019-08-31 | Research Associate (Institute of Technical Informatics)
Employment
Source: Self-asserted source
Tobias Scheipel

Education and qualifications (2)

Graz University of Technology: Graz, AT

2018-01 to 2022-12 | Doctor of Engineering Sciences (Dr.techn.) (Doctoral School Information and Communications Engineering)
Education
Source: Self-asserted source
Tobias Scheipel

Graz University of Technology: Graz, AT

2011-09 to 2017-05 | Dipl.-Ing. (Institute of Technical Informatics)
Education
Source: Self-asserted source
Tobias Scheipel

Works (19)

opoSoM: A Modular Measurement Platform for Dynamic Power Consumption of SoCs

27th Euromicro Conference Series on Digital System Design, Paris, France, 28/08/24
2024-08-20 | Conference paper | Author
SOURCE-WORK-ID:

899adbb5-3bfc-43e2-b7e8-feaed19fa85a

Contributors: Kristóf Kanics; Meinhard Kissich; Gerhard Wirrer; Tobias Scheipel; Marcel Carsten Baunach
Source: check_circle
TU Graz

Stitching FPGA Fabrics with FABulous and OpenLane 2

Proceedings of the 21st ACM International Conference on Computing Frontiers 2024 Workshops and Special Sessions, CF 2024 Companion
2024-07-01 | Conference paper | Author
SOURCE-WORK-ID:

c54f5096-6b96-4251-8429-1797efc27945

EID:

2-s2.0-85199147093

Part of ISBN: 9798400704925
Contributors: Leo Moser; Meinhard Kissich; Tobias Scheipel; Marcel Carsten Baunach
Source: check_circle
TU Graz

Fair and Starvation-Free Spinlock for Real-Time AUTOSAR Systems

Proceedings of the 39th ACM/SIGAPP Symposium On Applied Computing
2024-04-08 | Conference paper | Author
SOURCE-WORK-ID:

a12bce43-a8b3-48ea-a501-b8e29412f188

EID:

2-s2.0-85197731150

Part of ISBN: 9798400702433
Contributors: Drona Nagarajan; Tobias Scheipel; Marcel Carsten Baunach
Source: check_circle
TU Graz

One Solution to Rule Them All: ATTEST as Unified Testing Solution for Programming Courses

Proceedings in Tagungsband des FG-BS Herbsttreffens 2023
2023-09-28 | Conference paper | Author
SOURCE-WORK-ID:

9046d2b4-2d69-45c2-a8ef-92d0fcec68b6

Contributors: Meinhard Kissich; Kristóf Kanics; Klaus Weinbauer; Tobias Scheipel; Marcel Carsten Baunach
Source: check_circle
TU Graz

SmartOS: An OS Architecture for Sustainable Embedded Systems

Gesellschaft für Informatik e.V.
2022 | Conference paper
Source: Self-asserted source
Tobias Scheipel
grade
Preferred source (of 2)‎

Advances in Dynamic and Reconfigurable Embedded Systems Design

2022-12 | Dissertation/Thesis
Contributors: Tobias Scheipel
Source: Self-asserted source
Tobias Scheipel

Advances in Dynamic and Reconfigurable Embedded Systems Design

2022-12-19 | Dissertation/Thesis | Author
SOURCE-WORK-ID:

c80ea86f-74ba-46fb-b37a-308fb97667a8

Contributors: Tobias Scheipel
Source: check_circle
TU Graz

moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems

2022 25th Euromicro Conference on Digital System Design (DSD)
2022-08 | Conference paper
Contributors: Tobias Scheipel; Florian Angermair; Marcel Baunach
Source: Self-asserted source
Tobias Scheipel
grade
Preferred source (of 2)‎

A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime

2021 24th Euromicro Conference on Digital System Design (DSD)
2021-09 | Conference paper
Source: Self-asserted source
Tobias Scheipel
grade
Preferred source (of 2)‎

A Conversion Concept for a Legacy Software Model towards AUTOSAR Compliance

1st International Conference on Computing and Applied Engineering
2021-08-08 | Conference paper | Author
SOURCE-WORK-ID:

d42bb774-95f7-44db-a6c4-426d6eeae86a

Part of ISBN:

2320-2882

Contributors: Vimal Sivashanmugam; Tobias Scheipel; Marcel Carsten Baunach; Bhargav Adabala
Source: check_circle
TU Graz

papagenoReQ: Generation of Embedded Systems from Application Code Requirements

2021 International Conference on Electrical, Communication, and Computer Engineering (ICECCE)
2021-06-12 | Conference paper
Source: Self-asserted source
Tobias Scheipel
grade
Preferred source (of 2)‎

FPGA-based debugging with dynamic signal selection at run-time

CEUR Workshop Proceedings
2020 | Conference paper
EID:

2-s2.0-85082956774

Part of ISSN: 16130073
Contributors: Fiala, G.; Scheipel, T.; Neuwirth, W.; Baunach, M.
Source: Self-asserted source
Tobias Scheipel via Scopus - Elsevier
grade
Preferred source (of 2)‎

PapagenoX: Generation of electronics and logic for embedded systems from application software

SENSORNETS 2020 - Proceedings of the 9th International Conference on Sensor Networks
2020 | Conference paper
EID:

2-s2.0-85082989951

Contributors: Scheipel, T.; Baunach, M.
Source: Self-asserted source
Tobias Scheipel via Scopus - Elsevier
grade
Preferred source (of 2)‎

papagenoX: Generation of Electronics and Logic for Embedded Systems from Application Software

9th International Conference on Sensor Networks, Valletta, Malta, 28/02/20
2020-02-28 | Conference poster | Author
SOURCE-WORK-ID:

99b5befd-3ef6-44df-9c1b-c4ffb6e4a244

Contributors: Tobias Scheipel; Marcel Carsten Baunach
Source: check_circle
TU Graz

Towards an Automated Printed Circuit Board Generation Concept for Embedded Systems

International Journal on Advances in Systems and Measurements
2019-12 | Journal article
Source: Self-asserted source
Tobias Scheipel

papagenoPCB: An Automated Printed Circuit Board Generation Approach for Embedded Systems Prototyping

ICONS 2019 - The Fourteenth International Conference on Systems
2019-03-24 | Conference paper | Author
SOURCE-WORK-ID:

8b467b03-56f6-4809-96b3-81e1eb4a48ea

Part of ISBN: 978-1-61208-696-5
Part of ISBN: 978-1-61208-696-5
Contributors: Tobias Scheipel; Marcel Carsten Baunach
Source: check_circle
TU Graz

Smart mobility of the future – a challenge for embedded automotive systems

Elektrotechnik und Informationstechnik
2018-06-27 | Journal article | Author
SOURCE-WORK-ID:

410a5f43-c0fe-437e-8589-3a8a266c7500

EID:

2-s2.0-85049063350

Contributors: Marcel Carsten Baunach; Renata Martins Gomes; Maja Malenko; Fabian Mauroner; Leandro Batista Ribeiro; Tobias Scheipel
Source: check_circle
TU Graz
grade
Preferred source (of 2)‎

Einheit zur anwendungsbezogenen Leistungsmessung für die RISC-V-Architektur

Logistik und Echtzeit
2017 | Conference paper | Author
SOURCE-WORK-ID:

fec5db96-d281-4703-98fc-5397c6674164

EID:

2-s2.0-85037813664

Part of ISBN: 978-3-662-55784-6
Contributors: Tobias Scheipel; Fabian Mauroner; Marcel Carsten Baunach
Source: check_circle
TU Graz
grade
Preferred source (of 2)‎

System-Aware Performance Monitoring Unit for RISC-V Architectures

Proceedings of the 20th Euromicro Conference on Digital System Design (DSD)
2017-08-31 | Conference paper | Author
SOURCE-WORK-ID:

1038d132-0617-4d1a-9ca5-a75d6051a691

EID:

2-s2.0-85031400836

Contributors: Tobias Scheipel; Fabian Mauroner; Marcel Carsten Baunach
Source: check_circle
TU Graz
grade
Preferred source (of 2)‎