Personal information

No personal information available

Activities

Works (14)

Pragmatic Memory-System Support for Intermittent Computing Using Emerging Nonvolatile Memory

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2023-01 | Journal article
Contributors: Sivert T. Sliper; William Wang; Nikos Nikoleris; Alex S. Weddell; Anand Savanth; Pranay Prabhat; Geoff V. Merrett
Source: check_circle
Crossref

A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller

IEEE Journal of Solid-State Circuits
2021-02 | Journal article
Contributors: Benoit Labbe; Philex Fan; Thanusree Achuthan; Pranay Prabhat; Graham Peter Knight; James Myers
Source: check_circle
Crossref

Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

IEEE Journal of Solid-State Circuits
2019 | Journal article
Source: Self-asserted source
Pranay Prabhat

A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator With Forward-Body-Biasing

IEEE Solid-State Circuits Letters
2019-09 | Journal article
Part of ISSN: 2573-9603
Source: Self-asserted source
Pranay Prabhat
grade
Preferred source (of 3)‎

A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
2019-07 | Conference paper
Source: Self-asserted source
Pranay Prabhat

A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold Speedup

2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)
2018 | Conference paper
Source: Self-asserted source
Pranay Prabhat

A 12.4pJ/cycle sub-threshold, 16pJ/cycle near-threshold ARM Cortex-M0+ MCU with autonomous SRPG/DVFS and temperature tracking clocks

2017 Symposium on VLSI Circuits
2017 | Conference paper
Source: Self-asserted source
Pranay Prabhat

Evaluation and analysis of single-phase clock flip-flops for NTV applications

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
2017 | Conference paper
Source: Self-asserted source
Pranay Prabhat

Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
2017 | Conference paper
Source: Self-asserted source
Pranay Prabhat

A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator

IEEE Journal of Solid-State Circuits
2016 | Journal article
Source: Self-asserted source
Pranay Prabhat

Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem

2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
2016 | Conference paper
Source: Self-asserted source
Pranay Prabhat

8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
2015 | Conference paper
Source: Self-asserted source
Pranay Prabhat

Low power memory implementation for a GHz+ Dual Core ARM Cortex A9 processor on a high-K metal gate 32nm low power process

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test
2011 | Conference paper
Source: Self-asserted source
Pranay Prabhat

Biomedical instrumentation based on electrooculogram (EOG) signal processing and application to a hospital alarm system

Proceedings of 2005 International Conference on Intelligent Sensing and Information Processing, 2005.
2005 | Conference paper
Source: Self-asserted source
Pranay Prabhat