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Works (11)

A reduced device symmetrical-asymmetrical multilevel inverter with self capacitor voltage balancing and reduced capacitor voltage ripple

International Journal of Electronics
2025 | Journal article
Contributors: Anilkumar Chappa; Mudadla Dhananjaya; Vijaya Kumar J; V S Prasadarao K; A Hemachander; Durga Prasad Chinta
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Cascade control scheme for frequency control of wind-integrated multi-area multi-machine AC/DC-interlinked power system with deregulation

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Highly resilient 17‐level fault‐tolerant multilevel inverter topology with reduced capacitor size

International Journal of Circuit Theory and Applications
2024-06 | Journal article
Contributors: Anilkumar Chappa; Shubhrata Gupta; Lalit Kumar Sahu; Krishna Kumar Gupta; Hemachander Allamsetty
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Asymmetrical Multilevel Inverter Topology

10th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2022
2022 | Conference paper
EID:

2-s2.0-85152462591

Contributors: Chappa, A.; Seethala, G.; Rani Donpeudi, S.; Rambabu, C.
Source: Self-asserted source
ANILKUMAR CHAPPA via Scopus - Elsevier

Development of an Enhanced Selective Harmonic Elimination for a Single-Phase Multilevel Inverter with Staircase Modulation

Electronics
2022-11-25 | Journal article
Contributors: Govind S.; Anilkumar Chappa; K. Dhananjay Rao; Subhojit Dawn; Taha Selim Ustun
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Fault-Tolerant Asymmetrical Multilevel Inverter with Preserved Output Power under Post-Fault Operation

IEEE Transactions on Industrial Electronics
2021 | Journal article
Part of ISSN: 0278-0046
Part of ISSN: 1557-9948
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ANILKUMAR CHAPPA
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A Fault-Tolerant Multilevel Inverter Topology With Preserved Output Power and Voltage Levels Under Pre- and Postfault Operation

IEEE Transactions on Industrial Electronics
2021-07 | Journal article
Part of ISSN: 0278-0046
Part of ISSN: 1557-9948
Source: Self-asserted source
ANILKUMAR CHAPPA
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Symmetrical and Asymmetrical Reduced Device Multilevel Inverter Topology

IEEE Journal of Emerging and Selected Topics in Power Electronics
2021-02 | Journal article
Contributors: Anilkumar Chappa; Shubhrata Gupta; Lalit Kumar Sahu; Shivam Prakash Gautam; Krishna Kumar Gupta
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A Nine-Level Inverter Topology with Equal Source Utilization

IECON Proceedings (Industrial Electronics Conference)
2020 | Conference paper
EID:

2-s2.0-85097795015

Contributors: Chappa, A.; Gupta, S.; Sahu, L.K.; Kumar Gupta, K.
Source: Self-asserted source
ANILKUMAR CHAPPA via Scopus - Elsevier

Fault Diagnosis of Cascaded H-bridge Multilevel Inverter by DWPT Multi resolution and ANN

2020 1st International Conference on Power, Control and Computing Technologies, ICPC2T 2020
2020 | Conference paper
EID:

2-s2.0-85084292753

Contributors: Chappa, A.; Gupta, S.; Sahu, L.K.; Gupta, K.K.
Source: Self-asserted source
ANILKUMAR CHAPPA via Scopus - Elsevier

Resilient multilevel inverter topology with improved reliability

IET Power Electronics
2020-11 | Journal article
Contributors: Anilkumar Chappa; Shubhrata Gupta; Lalit Kumar Sahu; Krishna Kumar Gupta
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Peer review (18 reviews for 6 publications/grants)

Review activity for Computers & electrical engineering. (2)
Review activity for IEEE transactions on industrial electronics : (6)
Review activity for IEEE transactions on power delivery : (3)
Review activity for IEEE transactions on power electronics. (3)
Review activity for IET electric power applications / (1)
Review activity for IET power electronics. (3)