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Works (5)

An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2025-01 | Journal article
Contributors: Jinghai Wang; Shanlin Xiao; Jilong Luo; Bo Li; Lingfeng Zhou; Zhiyi Yu
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Crossref

Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2024 | Journal article
Contributors: Lingfeng Zhou; Shanlin Xiao; Huiyao Wang; Jinghai Wang; Zeyang Xu; Bohan Wang; Zhiyi Yu
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Crossref

Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2024 | Journal article
Contributors: Lingfeng Zhou; Shanlin Xiao; Huiyao Wang; Jinghai Wang; Zeyang Xu; Bohan Wang; Zhiyi Yu
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Crossref

LAC: A Novel Lightweight Asynchronous Controller With Optimized Phase Shift

IEEE Transactions on Circuits and Systems II: Express Briefs
2024-08 | Journal article
Contributors: Huiyao Wang; Shanlin Xiao; Lingfeng Zhou; Jinghai Wang; Zeyang Xu; Bohan Wang; Zhiyi Yu
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Crossref

Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement

2023 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)
2023-10-27 | Conference paper
Contributors: Zeyang Xu; Shanlin Xiao; Lingfeng Zhou; Bohan Wang; Zhiyi Yu
Source: Self-asserted source
Lingfeng Zhou