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Works (27)

Dataffinic computing: Data-centric architecture to support digital trust

Fujitsu Scientific and Technical Journal
2020 | Journal article
EID:

2-s2.0-85086070438

Part of ISBN:

00162523

Contributors: Tamura, M.; Yoshida, E.; Yamada, K.
Source: Self-asserted source
Eiji Yoshida via Scopus - Elsevier

Dynamic Traffic Control of Staging Traffic on the Interconnect of the HPC Cluster System

IEEE Access
2020 | Journal article
Part of ISSN: 2169-3536
Source: Self-asserted source
Eiji Yoshida

FairHym: Improving Inter-Process Fairness on Hybrid Memory Systems

Proceedings - 9th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2020
2020 | Conference paper
EID:

2-s2.0-85091990997

Contributors: Imamura, S.; Yoshida, E.
Source: Self-asserted source
Eiji Yoshida via Scopus - Elsevier

The Analysis of Inter-Process Interference on a Hybrid Memory System

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region Workshops
2020-01-15 | Conference paper
Source: Self-asserted source
Eiji Yoshida

POSTER: AR-MMAP: Write Performance Improvement of Memory-Mapped File

2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT)
2019-09 | Conference poster
Part of ISBN: 9781728136134
Source: Self-asserted source
Eiji Yoshida

Reducing CPU Power Consumption with Device Utilization-Aware DVFS for Low-Latency SSDs

IEICE Transactions on Information and Systems
2019-09-01 | Journal article
Contributors: Satoshi IMAMURA; Eiji YOSHIDA; Kazuichi OE
Source: Self-asserted source
Eiji Yoshida via JaLC

Data management system that facilitates the value creation cycle

Fujitsu Scientific and Technical Journal
2018 | Journal article
EID:

2-s2.0-85057994943

Part of ISBN:

00162523

Contributors: Matsubara, M.; Nakamura, M.; Sato, M.; Yoshida, E.; Matsuoka, N.
Source: Self-asserted source
Eiji Yoshida via Scopus - Elsevier

Reducing CPU Power Consumption for Low-Latency SSDs

2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA)
2018-08 | Conference paper
Source: Self-asserted source
Eiji Yoshida

Memory Expansion Technology for Large-Scale Data Processing Using Software-Controlled SSD

2018 IEEE Symposium on VLSI Circuits
2018-06 | Conference paper
Source: Self-asserted source
Eiji Yoshida

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE

IEEE Journal of Solid-State Circuits
2014-12 | Journal article
Part of ISSN: 0018-9200
Part of ISSN: 1558-173X
Source: Self-asserted source
Eiji Yoshida

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
2014-02 | Conference paper
Source: Self-asserted source
Eiji Yoshida

Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets

Japanese Journal of Applied Physics
2014-01-01 | Journal article
Part of ISSN: 0021-4922
Part of ISSN: 1347-4065
Source: Self-asserted source
Eiji Yoshida

Effects of Gate Line Width Roughness on Threshold-Voltage Fluctuation Among Short-Channel Transistors at High Drain Voltage

IEEE Electron Device Letters
2010-03 | Journal article
Part of ISSN: 0741-3106
Part of ISSN: 1558-0563
Source: Self-asserted source
Eiji Yoshida

A 45nm Low-Cost LSTP CMOS Technology with full NCS/dual-damascene Cu interconnects

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
2007 | Conference paper
Source: Self-asserted source
Eiji Yoshida

Continuous Scaling Methodology of Planar CMOS Transistors by Suppressing Fluctuation in Carrier Profile

2007 IEEE Symposium on VLSI Technology
2007-06 | Conference paper
Source: Self-asserted source
Eiji Yoshida

Performance Boost using a New Device Design Methodology Based on Characteristic Current for Low-Power CMOS

2006 International Electron Devices Meeting
2006 | Conference paper
Source: Self-asserted source
Eiji Yoshida
grade
Preferred source (of 2)‎

A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory

IEEE Transactions on Electron Devices
2006-04 | Journal article
Part of ISSN: 0018-9383
Source: Self-asserted source
Eiji Yoshida

Advanced Input/Output Technology Using Laterally Modulated Channel Metal–Oxide–Semiconductor Field Effect Transistor for 65-nm Node System on a Chip

Japanese Journal of Applied Physics
2006-04-25 | Journal article
Part of ISSN: 0021-4922
Part of ISSN: 1347-4065
Source: Self-asserted source
Eiji Yoshida

Advanced I/O Technology using Laterally Modulated Channel MOSFET for 65-nm Node SoC

Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials
2005 | Conference paper
Source: Self-asserted source
Eiji Yoshida

A study of highly scalable DG-FinDRAM

IEEE Electron Device Letters
2005-09 | Journal article
Part of ISSN: 0741-3106
Source: Self-asserted source
Eiji Yoshida

Impact of Thermal Budget Reduction on MOSFET Performance to Achieve High-speed and High-density DRAM-based System LSI

Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials
2002 | Conference paper
Source: Self-asserted source
Eiji Yoshida

Charging states of Si quantum dots as detected by AFM/Kelvin probe technique

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
2000 | Journal article
EID:

2-s2.0-0033700859

Part of ISBN:

00214922

Contributors: Shimizu, N.; Ikeda, M.; Yoshida, E.; Murakami, H.; Miyazaki, S.; Hirose, M.
Source: Self-asserted source
Eiji Yoshida via Scopus - Elsevier
grade
Preferred source (of 2)‎

Control of self-assembling formation of nanometer silicon dots by low pressure chemical vapor deposition

Thin Solid Films
2000 | Journal article
EID:

2-s2.0-0034226828

Part of ISBN:

00406090

Contributors: Miyazaki, S.; Hamamoto, Y.; Yoshida, E.; Ikeda, M.; Hirose, M.
Source: Self-asserted source
Eiji Yoshida via Scopus - Elsevier

Self-assembling of silicon quantum dots and its application to floating gate memory

1999 International Microprocesses and Nanotechnology Conference
1999 | Conference paper
EID:

2-s2.0-85043757603

Contributors: Miyazaki, S.; Murakami, H.; Ikeda, M.; Yoshida, E.; Kohno, A.; Hirose, M.
Source: Self-asserted source
Eiji Yoshida via Scopus - Elsevier

A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory

IEEE International Electron Devices Meeting 2003
Conference paper
Source: Self-asserted source
Eiji Yoshida

Direct measurement of carrier profiles in operating sub-30-nm N-MOSFETs

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.
Conference paper
Source: Self-asserted source
Eiji Yoshida

Scalability study on a capacitorless 1T-DRAM from single-gate PD-SOI to double-gate FinDRAM

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
Conference paper
Source: Self-asserted source
Eiji Yoshida