Personal information

processo, micro-archiecture, VLSI, ASIC
China

Activities

Employment (1)

Institute of Automation Chinese Academy of Sciences: Beijing, Beijing, CN

2009-07-05 to 2015 | Senior Engineer (National ASIC Design Engineering Center)
Employment
Source: Self-asserted source
谢少林

Education and qualifications (3)

Institute of Automation Chinese Academy of Sciences: Beijing, Beijing, CN

2006-09-01 to 2009-07-02 | Doctor (Applied Computer technology)
Education
Source: Self-asserted source
谢少林

Zhejiang University: Hangzhou, Zhejiang, CN

2004-09-05 to 2006-07-01 | Master (Information Department)
Education
Source: Self-asserted source
谢少林

Zhejiang University: Hangzhou, Zhejiang, CN

2000-09-05 to 2004-07-01 | Bechelor (Information Department)
Education
Source: Self-asserted source
谢少林

Works (1)

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator

IEEE Journal of Solid-State Circuits
2020-04 | Journal article
Contributors: Dong-Hyeon Park; Subhankar Pal; Siying Feng; Paul Gao; Jielun Tan; Austin Rovinski; Shaolin Xie; Chun Zhao; Aporva Amarnath; Timothy Wesley et al.
Source: check_circle
Crossref