Personal information

Greece

Activities

Employment (1)

Intel Germany GmbH: Munich, Bayern, DE

2016-01-15 to 2016-11-30 | Hardware Engineering (iCDG)
Employment
Source: Self-asserted source
Anastasios Psarras

Education and qualifications (3)

Democritus University of Thrace School of Engineering: Xanthi, Xanthi, GR

2014-02-01 to 2017-07-01 | PhD (Electrical and Computer Engineering)
Education
Source: Self-asserted source
Anastasios Psarras

Democritus University of Thrace School of Engineering: Xanthi, Xanthi, GR

2013-11-01 | MSc (Electrical and Computer Engineering)
Education
Source: Self-asserted source
Anastasios Psarras

Democritus University of Thrace School of Engineering: Xanthi, Xanthi, GR

2012-04-01 | Dipl Ing (Electrical and Computer Engineering)
Education
Source: Self-asserted source
Anastasios Psarras

Works (16)

The Mesochronous Dual-Clock FIFO Buffer

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2020-01 | Journal article
Contributors: Dimitrios Konstantinou; Anastasios Psarras; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos
Source: check_circle
Crossref

Low-power dual-edge-triggered synchronous latency-insensitive systems

2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)
2018-05 | Conference paper
Source: Self-asserted source
Anastasios Psarras

A Dual-Clock Multiple-Queue Shared Buffer

IEEE Transactions on Computers
2017 | Journal article
Contributors: Anastasios Psarras; Michalis Paschou; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos
Source: check_circle
Crossref

Networks-on-Chip With Double-Data-Rate Links

IEEE Transactions on Circuits and Systems I: Regular Papers
2017-12 | Journal article
Contributors: Anastasios Psarras; Savvas Moisidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos
Source: check_circle
Crossref

A Low-power network-on-chip architecture for tile-based chip multi-processors

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
2016 | Conference paper
EID:

2-s2.0-84974733264

Contributors: Psarras, A.; Lee, J.; Mattheakis, P.; Nicopoulos, C.; Dimitrakopoulos, G.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier

CrossOver: Clock domain crossing under virtual-channel flow control

Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
2016 | Conference paper
EID:

2-s2.0-84973636791

Contributors: Paschou, M.; Psarras, A.; Nicopoulos, C.; Dimitrakopoulos, G.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier

PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2016 | Journal article
EID:

2-s2.0-84968538415

Contributors: Psarras, A.; Lee, J.; Seitanidis, I.; Nicopoulos, C.; Dimitrakopoulos, G.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier

ShortPath: A network-on-chip router with fine-grained pipeline bypassing

IEEE Transactions on Computers
2016 | Journal article
EID:

2-s2.0-84987617565

Contributors: Psarras, A.; Seitanidis, I.; Nicopoulos, C.; Dimitrakopoulos, G.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier

ElastiNoC: A self-testable distributed VC-based network-on-chip architecture

Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014
2015 | Conference paper
EID:

2-s2.0-84922569992

Contributors: Seitanidis, I.; Psarras, A.; Kalligeros, E.; Nicopoulos, C.; Dimitrakopoulos, G.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier

ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2015 | Journal article
EID:

2-s2.0-84959487376

Contributors: Seitanidis, I.; Psarras, A.; Chrysanthou, K.; Nicopoulos, C.; Dimitrakopoulos, G.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier

Microarchitecture of network-on-chip routers: A designer’s perspective

Microarchitecture of Network-on-Chip Routers: A Designer's Perspective
2015 | Book
EID:

2-s2.0-84944212477

Contributors: Dimitrakopoulos, G.; Psarras, A.; Seitanidis, I.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier

PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation

Proceedings -Design, Automation and Test in Europe, DATE
2015 | Conference paper
EID:

2-s2.0-84945954378

Contributors: Psarras, A.; Seitanidis, I.; Nicopoulos, C.; Dimitrakopoulos, G.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier

Simulation of the dynamics of bacterial quorum sensing

IEEE Transactions on Nanobioscience
2015 | Journal article
EID:

2-s2.0-84930947848

Contributors: Psarras, A.I.; Karafyllidis, I.G.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier

Timing-resilient Network-on-Chip architectures

Proceedings of the 21st IEEE International On-Line Testing Symposium, IOLTS 2015
2015 | Conference paper
EID:

2-s2.0-84955454666

Contributors: Panteloukas, A.; Psarras, A.; Nicopoulos, C.; Dimitrakopoulos, G.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier

ElastiStore: An elastic buffer architecture for Network-on-Chip routers

Proceedings -Design, Automation and Test in Europe, DATE
2014 | Conference paper
EID:

2-s2.0-84903847734

Contributors: Seitanidis, I.; Psarras, A.; Dimitrakopoulos, G.; Nicopoulos, C.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier

Hardware primitives for the synthesis of multithreaded elastic systems

Proceedings -Design, Automation and Test in Europe, DATE
2014 | Conference paper
EID:

2-s2.0-84903834181

Contributors: Dimitrakopoulos, G.; Seitanidis, I.; Psarras, A.; Tsiouris, K.; Mattheakis, P.M.; Cortadella, J.
Source: Self-asserted source
Anastasios Psarras via Scopus - Elsevier