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Biography

Francesco Lorenzelli received his M.S. degree cum Laude in electrical engineering from Alma Mater Studiorum - Università di Bologna, Bologna, Italy. He is currently pursuing a Ph.D. degree with the Department of Electrical Engineering at KU Leuven and with IMEC, Leuven, Belgium, working on testing of quantum chips.
His research interests include Cell-Aware Test, Design-for-Test Technology, advanced packaging, quantum computing, electrical characterization and TCAD simulation of quantum devices.

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Works (7)

Test and Repair Improvements for UCIe

2024 IEEE European Test Symposium (ETS)
2024-05-20 | Conference paper
DOI: 10.1109/ets61313.2024.10567470
Contributors: Tsung-Hsuan Wang; Po-Yao Chuang; Francesco Lorenzelli; Erik Jan Marinissen
Source: Self-asserted source
Francesco Lorenzelli

Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures

2023 IEEE International Test Conference (ITC)
2023-10-07 | Conference paper
DOI: 10.1109/itc51656.2023.00031
Contributors: Francesco Lorenzelli; Asser Elsayed; Clement Godfrin; Alexander Grill; Stefan Kubicek; Ruoyu Li; Michele Stucchi; Danny Wan; Kristiaan De Greve; Erik Jan Marinissen et al.
Source: Self-asserted source
Francesco Lorenzelli

Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency

2023 IEEE International Test Conference in Asia (ITC-Asia)
2023-09-12 | Conference paper
DOI: 10.1109/itc-asia58802.2023.10301169
Contributors: Po-Yao Chuang; Francesco Lorenzelli; Erik Jan Marinissen
Source: Self-asserted source
Francesco Lorenzelli

Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications

2023 IEEE European Test Symposium (ETS)
2023-05-22 | Conference paper
DOI: 10.1109/ets56758.2023.10173954
Contributors: Francesco Lorenzelli; Asser Elsayed; Clement Godfrin; Alexander Grill; Stefan Kubicek; Ruoyu Li; Michele Stucchi; Danny Wan; Kristiaan De Greve; Erik Jan Marinissen et al.
Source: Self-asserted source
Francesco Lorenzelli

Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages

2023 IEEE International 3D Systems Integration Conference (3DIC)
2023-05-10 | Conference paper | Writing - review & editing
DOI: 10.1109/3dic57175.2023.10154900
Contributors: Po-Yao Chuang; Francesco Lorenzelli; Sreejit Chakravarty; Slimane Boutobza; Cheng-Wen Wu; Georges Gielen; Erik Jan Marinissen; Francesco Lorenzelli
Source: Self-asserted source
Francesco Lorenzelli

Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages

2023 IEEE 41st VLSI Test Symposium (VTS)
2023-04-24 | Conference paper | Writing - review & editing
DOI: 10.1109/vts56346.2023.10140006
Contributors: Po-Yao Chuang; Francesco Lorenzelli; Sreejit Chakravarty; Cheng-Wen Wu; Georges Gielen; Erik Jan Marinissen; Francesco Lorenzelli
Source: Self-asserted source
Francesco Lorenzelli

Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis

2021 IEEE European Test Symposium (ETS)
2021-05-24 | Conference paper | Writing - original draft, Writing - review & editing
DOI: 10.1109/ets50041.2021.9465469
Contributors: Francesco Lorenzelli; Zhan Gao; Joe Swenton; Santosh Malagi; Erik Jan Marinissen; Francesco Lorenzelli
Source: Self-asserted source
Francesco Lorenzelli
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