Personal information

Websites & social links

Linkedin

Activities

Collapse all

Education and qualifications (3)

Nanyang Technological University: Singapore, Singapore, SG

2019-07 to present | PhD (EEE)
Education
Source: Self-asserted source
Juncheng Chen

Technical University of Munich & Nanyang Technological University Singapore: Singapore , SG

2017-08 to 2019-06 | Master of Science in Integrated Circuit Design (EEE)
Education
Source: Self-asserted source
Juncheng Chen

Guangdong University of Technology: Guangzhou, Guangdong, CN

2013-09 to 2017-06 | Bachelor of Engineering (School of Information Engineering )
Education
Source: Self-asserted source
Juncheng Chen

Professional activities (1)

IEEE: Singapore, Others, SG

Student Member
Membership
Source: Self-asserted source
Juncheng Chen

Works (10)

Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2024 | Journal article
DOI: 10.1109/TVLSI.2024.3409650
Contributors: Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Kwen-Siong Chong; Bah-Hwee Gwee
Source: check_circle
Crossref

Incremental Linear Regression Attack

2022 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)
2022-12-14 | Journal article
DOI: 10.1109/asianhost56390.2022.10022167
Contributors: Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Zhili Zou; Kwen-Siong Chong; Zhiping Lin; Bah-Hwee Gwee
Source: Self-asserted source
Juncheng Chen

A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2022-09 | Journal article
DOI: 10.1109/TVLSI.2022.3175180
Contributors: Jun-Sheng Ng; Juncheng Chen; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee
Source: check_circle
Crossref

An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations

2022 IEEE International Symposium on Circuits and Systems (ISCAS)
2022-05-28 | Conference paper
DOI: 10.1109/iscas48785.2022.9937684
Contributors: Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Joseph Chang; Bah-Hwee Gwee
Source: Self-asserted source
Juncheng Chen

Non-profiling based Correlation Optimization Deep Learning Analysis

2022 IEEE International Symposium on Circuits and Systems (ISCAS)
2022-05-28 | Conference paper
DOI: 10.1109/iscas48785.2022.9937217
Contributors: Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Zhiping Lin; Joseph Sylvester Chang; Bah-Hwee Gwee
Source: Self-asserted source
Juncheng Chen

A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures

IEEE Transactions on Information Forensics and Security
2021 | Journal article
DOI: 10.1109/TIFS.2021.3093783
Contributors: Juncheng Chen; Jun-Sheng Ng; Kwen-Siong Chong; Zhiping Lin; Bah-Hwee Gwee
Source: check_circle
Crossref

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation

IEEE Journal on Emerging and Selected Topics in Circuits and Systems
2021-06 | Journal article
DOI: 10.1109/jetcas.2021.3077887
Part of ISSN: 2156-3357
Part of ISSN: 2156-3365
Contributors: Kwen-Siong Chong; Jun Sheng Ng; Juncheng Chen; NE KYAW ZWA LWIN; Nay Aung Kyaw; Weng-Geng Ho; Joseph Chang; Bah Hwee Gwee
Source: Self-asserted source
Juncheng Chen

Normalized Differential Power Analysis - for Ghost Peaks Mitigation

2021 IEEE International Symposium on Circuits and Systems (ISCAS)
2021-05 | Conference paper
DOI: 10.1109/iscas51556.2021.9401487
Contributors: Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Zhiping Lin; Joseph Sylvester Chang; Bah-Hwee Gwee
Source: Self-asserted source
Juncheng Chen

A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications

2020 IEEE International Symposium on Circuits and Systems (ISCAS)
2020-10 | Conference paper
DOI: 10.1109/iscas45731.2020.9180849
Contributors: Weng-Geng Ho; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Jun-Sheng Ng; Juncheng Chen; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang
Source: Self-asserted source
Juncheng Chen

A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES)

2020 IEEE International Symposium on Circuits and Systems (ISCAS)
2020-10 | Conference paper
DOI: 10.1109/iscas45731.2020.9180778
Contributors: Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee
Source: Self-asserted source
Juncheng Chen
How many people are using ORCID?