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Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking

IEEE Access
2020 | Journal article
Contributors: Subhajit Das; Arun Kumar Sunaniya; Reshmi Maity; Niladri Pratap Maity
Source: check_circle
Crossref

Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach (Circuits, Systems, and Signal Processing, (2018), 37, 4, (1575-1593), 10.1007/s00034-017-0609-3)

Circuits, Systems, and Signal Processing
2018 | Journal article
EID:

2-s2.0-85056881145

Contributors: Das, S.; Ghosh, S.; Das, N.; Maity, S.P.; Rahaman, H.; Maity, R.; Maity, N.
Source: Self-asserted source
Subhajit Das via Scopus - Elsevier

Hardware implementation of adaptive feedback based reversible image watermarking for image processing application

Microsystem Technologies
2018 | Journal article
EID:

2-s2.0-85049603848

Contributors: Das, S.; Singh, P.; Koley, C.
Source: Self-asserted source
Subhajit Das via Scopus - Elsevier

VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach

Circuits, Systems, and Signal Processing
2018 | Journal article
EID:

2-s2.0-85043449297

Contributors: Das, S.; Maity, R.; Maity, N.P.
Source: Self-asserted source
Subhajit Das via Scopus - Elsevier

An adaptive feedback based reversible watermarking algorithm using difference expansion

2015 IEEE 2nd International Conference on Recent Trends in Information Systems, ReTIS 2015 - Proceedings
2015 | Conference paper
EID:

2-s2.0-84954160347

Contributors: Ghosh, S.; Das, N.; Das, S.; Maity, S.P.; Rahaman, H.
Source: Self-asserted source
Subhajit Das via Scopus - Elsevier

FPGA and SoC based VLSI architecture of reversible watermarking using rhombus interpolation by difference expansion

11th IEEE India Conference: Emerging Trends and Innovation in Technology, INDICON 2014
2015 | Conference paper
EID:

2-s2.0-84924091703

Contributors: Ghosh, S.; Das, N.; Das, S.; Maity, S.P.; Rahaman, H.
Source: Self-asserted source
Subhajit Das via Scopus - Elsevier

Digital design and pipelined architecture for reversible watermarking based on difference expansion using FPGA

Proceedings - 2014 13th International Conference on Information Technology, ICIT 2014
2014 | Conference paper
EID:

2-s2.0-84946693145

Contributors: Ghosh, S.; Das, N.; Das, S.; Maity, S.P.; Rahaman, H.
Source: Self-asserted source
Subhajit Das via Scopus - Elsevier