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Bangladesh, Malaysia

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Employment (1)

American International University-Bangladesh: Dhaka, BD

2003-07-01 to present | Associate Professor (Electrical and Electronic Engineering)
Employment
Source: Self-asserted source
Shahriyar Masud Rizvi

Education and qualifications (3)

Universiti Teknologi Malaysia: Johor Bahru, Johor, MY

2017-10 to 2023-04 | PhD (Electrical Engineering)
Education
Source: Self-asserted source
Shahriyar Masud Rizvi

University of Wyoming: Laramie, WY, US

2000-09 to 2002-12 | MS (Electrical Engineering)
Education
Source: Self-asserted source
Shahriyar Masud Rizvi

University of Wyoming: Laramie, WY, US

1997-08 to 2000-08 | BS (Electrical Engineering)
Education
Source: Self-asserted source
Shahriyar Masud Rizvi

Works (9)

Computation and memory optimized spectral domain convolutional neural network for throughput and energy-efficient inference

Applied Intelligence
2023-02 | Journal article
DOI: 10.1007/s10489-022-03756-1
Contributors: Shahriyar Masud Rizvi; Ab Al-Hadi Ab Rahman; Usman Ullah Sheikh; Kazi Ahmed Asif Fuad; Hafiz Muhammad Faisal Shehzad
Source: check_circle
Crossref

A Compact Spectral Model for Convolutional Neural Network

Future Technologies Conference (FTC) 2022
2022-10 | Conference paper
Contributors: Sayed Omid Ayat; Shahriyar Masud Rizvi; Hamdan Abdellatef; Ab Al-Hadi Ab Rahman; Shahidatul Sadiah Abdul Manan
Source: Self-asserted source
Shahriyar Masud Rizvi

A low-complexity complex-valued activation function for fast and accurate spectral domain convolutional neural network

Indonesian Journal of Electrical Engineering and Informatics (IJEEI)
2021 | Journal article
Source: Self-asserted source
Shahriyar Masud Rizvi

Hardware Software Co-Simulation of Canny Edge Detection Algorithm

International Journal of Computer Applications (IJCA)
2015 | Journal article
Source: Self-asserted source
Shahriyar Masud Rizvi

Varying Sample-Width to Realize Area-Efficient FPGA Realization of Sobel-Fieldman Edge Detector

AIUB Journal of Science and Engineering (AJSE)
2015 | Journal article
Source: Self-asserted source
Shahriyar Masud Rizvi

Tools and Techniques for Safe Synthesis of FSMDs Represented in Behavioral Level Implicit Style Verilog HDL or VHDL

FPGA Designer Forum (at Southern Programmable Logic (SPL) Conference)
2007 | Conference paper
Source: Self-asserted source
Shahriyar Masud Rizvi

A Methodology for Retaining Pre-Synthesis Behavior of FSMs modeled in Implicit Style Verilog HDL after Synthesis and Implementation

Jahangirnagar University Journal of Electronics and Computer Science (JUJECS)
2006 | Journal article
Source: Self-asserted source
Shahriyar Masud Rizvi

A Methodology to Remove Unwanted Delays in Outputs and Pre and Post-Synthesis Simulation Mismatches in Implicit State Machines

Electronic Design Processes (EDP) Workshop
2004 | Conference paper
Source: Self-asserted source
Shahriyar Masud Rizvi

Guidelines for Safe Synthesis of While Loops In Implicit Style Verilog HDL

International Conference on Electrical and Computer Engineering (ICECE)
2004 | Conference paper
Source: Self-asserted source
Shahriyar Masud Rizvi
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