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Low Complexity Reconfigurable-Scalable Architecture Design Methodology for Deep Neural Network Inference Accelerator

2022 IEEE 35th International System-on-Chip Conference (SOCC)
2022-09-05 | Conference paper
Contributors: Anagha Nimbekar; Chandrasekhara Srinivas Vatti; Y V Sai Dinesh; Sunidhi Singh; Tarun Gupta; Ramesh Reddy Chandrapu; Amit Acharyya
Source: Self-asserted source
Sai Dinesh Y V

VLSI Architecture Design Methodology for Deep learning based Upper Limb and Lower Limb Movement Classification for Rehabilitation Application

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)
2022-03-01 | Conference paper
Contributors: Anagha Nimbekar; Y V Sai Dinesh; Arvind Gautam; Vidhumouli Hunsigida; Appa Rao Nali; Amit Acharyya
Source: Self-asserted source
Sai Dinesh Y V