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Works (34)

A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2025-03 | Journal article
DOI: 10.1109/TVLSI.2024.3472073
Contributors: Jonghyun Oh; Kwanseo Park; Young-Ha Hwang
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A 0.09-pJ/b/dB 28-Gb/s Digital CDR With ISI-Resistant Phase Detector

IEEE Transactions on Circuits and Systems II: Express Briefs
2024 | Journal article
DOI: 10.1109/TCSII.2024.3440584
Contributors: Suil Kang; Dongwoo Kang; Sinho Lee; Minkyo Shim; Seungha Roh; Sunjin Choi; Kwanseo Park
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A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS

IEEE Transactions on Circuits and Systems I: Regular Papers
2024 | Journal article
DOI: 10.1109/TCSI.2024.3391173
Contributors: Minkyo Shim; Seungha Roh; Yunhee Lee; Jung-Woo Sull; Deog-Kyoon Jeong; Kwanseo Park
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A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR

IEEE Transactions on Circuits and Systems I: Regular Papers
2024 | Journal article
DOI: 10.1109/TCSI.2024.3393436
Contributors: Seungha Roh; Minkyo Shim; Yoojin Jung; Deog-Kyoon Jeong; Kwanseo Park
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Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery

IEEE Transactions on Circuits and Systems II: Express Briefs
2024 | Journal article
DOI: 10.1109/TCSII.2023.3335103
Contributors: Young-Ha Hwang; Kwanseo Park
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A 3×12 -Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs
2024-11 | Journal article
DOI: 10.1109/TCSII.2024.3442200
Contributors: Dongwoo Kang; Han-Gon Ko; Kwanseo Park
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A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link

IEEE Access
2023 | Journal article
DOI: 10.1109/ACCESS.2023.3275441
Contributors: Minkyo Shim; Woonghee Lee; Yunhee Lee; Kwanseo Park; Deog-Kyoon Jeong
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A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

IEEE Journal of Solid-State Circuits
2023-05 | Journal article
DOI: 10.1109/JSSC.2022.3212541
Contributors: Woosong Jung; Kwangho Lee; Kwanseo Park; Haram Ju; Jinhyung Lee; Deog-Kyoon Jeong
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A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation

IEEE Transactions on Circuits and Systems II: Express Briefs
2023-02 | Journal article
DOI: 10.1109/TCSII.2022.3212082
Contributors: Minkyo Shim; Kwang-Hoon Lee; Seungha Roh; Kwanseo Park; Deog-Kyoon Jeong
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Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

IEEE Journal of Solid-State Circuits
2022-10 | Journal article
DOI: 10.1109/JSSC.2022.3189663
Contributors: Haram Ju; Kwangho Lee; Kwanseo Park; Woosong Jung; Deog-Kyoon Jeong
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Design Techniques for a 6.4–32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency–Phase Detector

IEEE Journal of Solid-State Circuits
2022-02 | Journal article
DOI: 10.1109/JSSC.2021.3116485
Contributors: Kwanseo Park; Minkyo Shim; Han-Gon Ko; Borivoje Nikolic; Deog-Kyoon Jeong
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An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

IEEE Journal of Solid-State Circuits
2022-01 | Journal article
DOI: 10.1109/JSSC.2021.3109562
Contributors: Zhongkai Wang; Minsoo Choi; Kyoungtae Lee; Kwanseo Park; Zhaokai Liu; Ayan Biswas; Jaeduk Han; Sijun Du; Elad Alon
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A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS

IEEE Access
2021 | Journal article
DOI: 10.1109/ACCESS.2021.3125274
Contributors: Byungjun Kang; Gyu-Seob Jeong; Jeongho Hwang; Kwanseo Park; Hyungrok Do; Hyojun Kim; Han-Gon Ko; Moon-Chul Choi; Deog-Kyoon Jeong
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A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration

IEEE Journal of Solid-State Circuits
2021-08 | Journal article
DOI: 10.1109/JSSC.2021.3062554
Contributors: Min-Seong Choo; Sungwoo Kim; Han-Gon Ko; Sung-Yong Cho; Kwanseo Park; Jinhyung Lee; Soyeong Shin; Hankyu Chi; Deog-Kyoon Jeong
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A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

IEEE Journal of Solid-State Circuits
2021-05 | Journal article
DOI: 10.1109/JSSC.2020.3030816
Contributors: Kwanseo Park; Kwangho Lee; Sung-Yong Cho; Jinhyung Lee; Jeongho Hwang; Min-Seong Choo; Deog-Kyoon Jeong
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An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs
2021-02 | Journal article
DOI: 10.1109/TCSII.2020.3014925
Contributors: Kwangho Lee; Hyojun Kim; Woosong Jung; Jinhyung Lee; Haram Ju; Kwanseo Park; Ook Kim; Deog-Kyoon Jeong
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A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

IEEE Journal of Solid-State Circuits
2020-08 | Journal article
DOI: 10.1109/JSSC.2020.2987690
Contributors: Jinhyung Lee; Kwangho Lee; Hyojun Kim; Byungmin Kim; Kwanseo Park; Deog-Kyoon Jeong
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Analysis of frequency detection capability of Alexander phase detector

Electronics Letters
2020-02 | Journal article
DOI: 10.1049/el.2019.3488
Contributors: Kwanseo Park; Deog‐Kyoon Jeong
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A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response

IEEE Transactions on Circuits and Systems II: Express Briefs
2019-12 | Journal article
DOI: 10.1109/TCSII.2019.2949555
Contributors: Min-Seong Choo; Yeonggeun Song; Sung-Yong Cho; Han-Gon Ko; Kwanseo Park; Deog-Kyoon Jeong
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A 2.5–28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver

IEEE Transactions on Circuits and Systems II: Express Briefs
2019-12 | Journal article
DOI: 10.1109/TCSII.2019.2949173
Contributors: Moon-Chul Choi; Sung-Yong Cho; Minkyo Shim; Byungmin Kim; Han-Gon Ko; Haram Ju; Kwanseo Park; Hyojun Kim; Kwandong Kim; Deog-Kyoon Jeong
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A Modulo-FIR Equalizer for Wireline Communications

IEEE Transactions on Circuits and Systems I: Regular Papers
2019-11 | Journal article
DOI: 10.1109/TCSI.2019.2923636
Contributors: Gyu-Seob Jeong; Byungjun Kang; Haram Ju; Kwanseo Park; Deog-Kyoon Jeong
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A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

IEEE Journal of Solid-State Circuits
2019-10 | Journal article
DOI: 10.1109/JSSC.2019.2917833
Contributors: Min-Seong Choo; Kwanseo Park; Han-Gon Ko; Sung-Yong Cho; Kwangho Lee; Deog-Kyoon Jeong
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25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections

IEEE Transactions on Circuits and Systems II: Express Briefs
2018-10 | Journal article
DOI: 10.1109/TCSII.2018.2850663
Contributors: Gyu-Seob Jeong; Jeongho Hwang; Hong-Seok Choi; Hyungrok Do; Daehyun Koh; Daeyoung Yun; Jinhyung Lee; Kwanseo Park; Han-Gon Ko; Kwangho Lee et al.
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A 2.44-pJ/b 1.62–10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE

IEEE Transactions on Circuits and Systems II: Express Briefs
2018-10 | Journal article
DOI: 10.1109/TCSII.2018.2846677
Contributors: Jinhyung Lee; Kwanseo Park; Kwangho Lee; Deog-Kyoon Jeong
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A 6.7–11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

IEEE Journal of Solid-State Circuits
2018-10 | Journal article
DOI: 10.1109/JSSC.2018.2859947
Contributors: Kwanseo Park; Woorham Bae; Jinhyung Lee; Jeongho Hwang; Deog-Kyoon Jeong
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A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel

IEEE Transactions on Circuits and Systems II: Express Briefs
2017 | Journal article
DOI: 10.1109/tcsii.2017.2747148
Part of ISSN: 1549-7747
Contributors: Kwanseo Park; Jinhyung Lee; Kwangho Lee; Min-Seong Choo; Sungchun Jang; Sang-Hyeok Chu; Sungwoo Kim; Deog-Kyoon Jeong
Source: Self-asserted source
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A Supply-Scalable Serializing Transmitter with Controllable Output Swing and Equalization for Next Generation Standards

IEEE Transactions on Industrial Electronics
2017 | Journal article
DOI: 10.1109/tie.2017.2779439
Part of ISSN: 0278-0046
Contributors: Woorham Bae; Haram Ju; Kwanseo Park; Jaeduk Han; Deog-Kyoon Jeong
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Kwanseo Park via Crossref Metadata Search

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control

2017 IEEE Custom Integrated Circuits Conference (CICC)
2017-04 | Conference paper
DOI: 10.1109/cicc.2017.7993599
Part of ISBN: 9781509051915
Contributors: Kwanseo Park; Woorham Bae; Deog-Kyoon Jeong
Source: Self-asserted source
Kwanseo Park via Crossref Metadata Search

A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)
2016-11 | Conference paper
DOI: 10.1109/asscc.2016.7844180
Part of ISBN: 9781509036998
Contributors: Woorham Bae; Haram Ju; Kwanseo Park; Deog-Kyoon Jeong
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A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

IEEE Journal of Solid-State Circuits
2016-10 | Journal article
DOI: 10.1109/jssc.2016.2579159
Part of ISSN: 0018-9200
Contributors: Woorham Bae; Haram Ju; Kwanseo Park; Sung-Yong Cho; Deog-Kyoon Jeong
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Kwanseo Park via Crossref Metadata Search

A 0.36 pJ/bit, 0.025 mm<inline-formula> <tex-math notation="LaTeX">${}^{\text{2}}$</tex-math> </inline-formula>, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology

IEEE Transactions on Circuits and Systems I: Regular Papers
2016-09 | Journal article
DOI: 10.1109/tcsi.2016.2578960
Part of ISSN: 1549-8328
Contributors: Woorham Bae; Gyu-Seob Jeong; Kwanseo Park; Sung-Yong Cho; Yoonsoo Kim; Deog-Kyoon Jeong
Source: Self-asserted source
Kwanseo Park via Crossref Metadata Search

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS

2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)
2015-11 | Conference paper
DOI: 10.1109/asscc.2015.7387448
Part of ISBN: 9781467371919
Contributors: Woorham Bae; Haram Ju; Kwanseo Park; Sung-Yong Cho; Deog-Kyoon Jeong
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A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS

2015 IEEE International Symposium on Circuits and Systems (ISCAS)
2015-05 | Conference paper
DOI: 10.1109/iscas.2015.7169165
Part of ISBN: 9781479983919
Contributors: Kwanseo Park; Woorham Bae; Haram Ju; Jinhyung Lee; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong
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A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)
2014-09 | Conference paper
DOI: 10.1109/esscirc.2014.6942118
Part of ISBN: 9781479956968
Contributors: Woorham Bae; Gyu-Seob Jeong; Kwanseo Park; Sung-Yong Cho; Yoonsoo Kim; Deog-Kyoon Jeong
Source: Self-asserted source
Kwanseo Park via Crossref Metadata Search

Peer review (2 reviews for 2 publications/grants)

Review activity for AEÜ. (1)
Review activity for Results in engineering. (1)
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