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Communication Optimization for Distributed Execution of Graph Neural Networks

2023 IEEE International Parallel and Distributed Processing Symposium (IPDPS)
2023-05 | Conference paper
DOI: 10.1109/ipdps54959.2023.00058
Contributors: Süreyya Emre Kurt; Jinghua Yan; Aravind Sukumaran-Rajam; Prashant Pandey; P. Sadayappan
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

Training of deep learning pipelines on memory-constrained GPUs via segmented fused-tiled execution

Proceedings of the 31st ACM SIGPLAN International Conference on Compiler Construction
2022-03-19 | Conference paper | Author
DOI: 10.1145/3497776.3517766
Contributors: Yufan Xu; SAURABH MANISH RAJE; Atanas Rountev; Gerald Sabin; Aravind Sukumaran Rajam; Ponnuswamy Sadayappan
Source: Self-asserted source
Ponnuswamy Sadayappan

Automated derivation of parametric data movement lower bounds for affine programs

Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, PLDI 2020, London, UK, June 15-20, 2020
2020 | Conference paper
Source: Self-asserted source
Ponnuswamy Sadayappan

A Code Generator for High-Performance Tensor Contractions on GPUs

IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2019, Washington, DC, USA, February 16-20, 2019
2019 | Conference paper
DOI: 10.1109/CGO.2019.8661182
Source: Self-asserted source
Ponnuswamy Sadayappan

Adaptive sparse tiling for sparse matrix multiplication

Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2019, Washington, DC, USA, February 16-20, 2019
2019 | Conference paper
DOI: 10.1145/3293883.3295712
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
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An efficient mixed-mode representation of sparse tensors

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2019, Denver, Colorado, USA, November 17-19, 2019
2019 | Conference paper
Source: Self-asserted source
Ponnuswamy Sadayappan

Load-Balanced Sparse MTTKRP on GPUs

2019 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2019, Rio de Janeiro, Brazil, May 20-24, 2019
2019 | Conference paper
Source: Self-asserted source
Ponnuswamy Sadayappan

On Optimizing Complex Stencils on GPUs

2019 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2019, Rio de Janeiro, Brazil, May 20-24, 2019
2019 | Conference paper
DOI: 10.1109/IPDPS.2019.00073
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 3)‎

Analytical modeling of cache behavior for affine programs

Proc. ACM Program. Lang.
2018 | Journal article
DOI: 10.1145/3158120
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 3)‎

Associative instruction reordering to alleviate register pressure

Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis, SC 2018, Dallas, TX, USA, November 11-16, 2018
2018 | Conference paper
Source: Self-asserted source
Ponnuswamy Sadayappan

Associative instruction reordering to alleviate register pressure

Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis, SC 2018, Dallas, TX, USA, November 11-16, 2018
2018 | Conference paper
Source: Self-asserted source
Ponnuswamy Sadayappan

Domain-Specific Optimization and Generation of High-Performance GPU Code for Stencil Computations

Proceedings of the IEEE
2018 | Journal article
DOI: 10.1109/JPROC.2018.2862896
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 3)‎

Efficient sparse-matrix multi-vector product on GPUs

Proceedings of the 27th International Symposium on High-Performance Parallel and Distributed Computing, HPDC 2018, Tempe, AZ, USA, June 11-15, 2018
2018 | Conference paper
DOI: 10.1145/3208040.3208062
Source: Self-asserted source
Ponnuswamy Sadayappan

GPU code optimization using abstract kernel emulation and sensitivity analysis

Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2018, Philadelphia, PA, USA, June 18-22, 2018
2018 | Conference paper
DOI: 10.1145/3192366.3192397
Source: Self-asserted source
Ponnuswamy Sadayappan

Optimizing Tensor Contractions in CCSD(T) for Efficient Execution on GPUs

Proceedings of the 32nd International Conference on Supercomputing, ICS 2018, Beijing, China, June 12-15, 2018
2018 | Conference paper
DOI: 10.1145/3205289.3205296
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 3)‎

Parallel Latent Dirichlet Allocation on GPUs

Computational Science - ICCS 2018 - 18th International Conference, Wuxi, China, June 11-13, 2018, Proceedings, Part II
2018 | Conference paper
DOI: 10.1007/978-3-319-93701-4\_20
Source: Self-asserted source
Ponnuswamy Sadayappan

Register optimizations for stencils on GPUs

Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2018, Vienna, Austria, February 24-28, 2018
2018 | Conference paper
DOI: 10.1145/3178487.3178500
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 3)‎

Sampled Dense Matrix Multiplication for High-Performance Machine Learning

25th IEEE International Conference on High Performance Computing, HiPC 2018, Bengaluru, India, December 17-20, 2018
2018 | Conference paper
DOI: 10.1109/HiPC.2018.00013
Source: Self-asserted source
Ponnuswamy Sadayappan

TTLG - An Efficient Tensor Transposition Library for GPUs

2018 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2018, Vancouver, BC, Canada, May 21-25, 2018
2018 | Conference paper
Source: Self-asserted source
Ponnuswamy Sadayappan

MultiGraph: Efficient Graph Processing on GPUs

26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017, Portland, OR, USA, September 9-13, 2017
2017 | Conference paper
DOI: 10.1109/PACT.2017.48
Source: Self-asserted source
Ponnuswamy Sadayappan

On improving performance of sparse matrix-matrix multiplication on GPUs

Proceedings of the International Conference on Supercomputing, ICS 2017, Chicago, IL, USA, June 14-16, 2017
2017 | Conference paper
DOI: 10.1145/3079079.3079106
Source: Self-asserted source
Ponnuswamy Sadayappan

Optimizing the Four-Index Integral Transform Using Data Movement Lower Bounds Analysis

Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Austin, TX, USA, February 4-8, 2017
2017 | Conference paper
Source: Self-asserted source
Ponnuswamy Sadayappan

Optimizing the Four-Index Integral Transform Using Data Movement Lower Bounds Analysis

Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Austin, TX, USA, February 4-8, 2017
2017 | Conference paper
Source: Self-asserted source
Ponnuswamy Sadayappan

A domain-specific compiler for a parallel multiresolution adaptive numerical simulation environment

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2016, Salt Lake City, UT, USA, November 13-18, 2016
2016 | Conference paper
DOI: 10.1109/SC.2016.39
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

Effective padding of multidimensional arrays to avoid cache conflict misses

Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2016, Santa Barbara, CA, USA, June 13-17, 2016
2016 | Conference paper
DOI: 10.1145/2908080.2908123
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

On fusing recursive traversals of K-d trees

Proceedings of the 25th International Conference on Compiler Construction, CC 2016, Barcelona, Spain, March 12-18, 2016
2016 | Conference paper
DOI: 10.1145/2892208.2892228
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

PolyCheck: dynamic verification of iteration space transformations on affine programs

Proceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2016, St. Petersburg, FL, USA, January 20 - 22, 2016
2016 | Conference paper
DOI: 10.1145/2837614.2837656
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

Resource Conscious Reuse-Driven Tiling for GPUs

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, PACT 2016, Haifa, Israel, September 11-15, 2016
2016 | Conference paper
DOI: 10.1145/2967938.2967967
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

Distributed memory code generation for mixed Irregular/Regular computations

Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2015, San Francisco, CA, USA, February 7-11, 2015
2015 | Conference paper
DOI: 10.1145/2688500.2688515
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

On Characterizing the Data Access Complexity of Programs

Proceedings of the 42nd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2015, Mumbai, India, January 15-17, 2015
2015 | Conference paper
DOI: 10.1145/2676726.2677010
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

On optimizing machine learning workloads via kernel fusion

Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2015, San Francisco, CA, USA, February 7-11, 2015
2015 | Conference paper
DOI: 10.1145/2688500.2688521
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

A Communication-Optimal Framework for Contracting Distributed Tensors

International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2014, New Orleans, LA, USA, November 16-21, 2014
2014 | Conference paper
DOI: 10.1109/SC.2014.36
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

A framework for enhancing data reuse via associative reordering

ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '14, Edinburgh, United Kingdom - June 09 - 11, 2014
2014 | Conference paper
DOI: 10.1145/2594291.2594342
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

Automatic parallelization of a class of irregular loops for distributed memory systems

ACM Trans. Parallel Comput.
2014 | Journal article
DOI: 10.1145/2660251
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

Compiler-assisted detection of transient memory errors

ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '14, Edinburgh, United Kingdom - June 09 - 11, 2014
2014 | Conference paper
DOI: 10.1145/2594291.2594298
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

Hybrid Hexagonal/Classical Tiling for GPUs

12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2014, Orlando, FL, USA, February 15-19, 2014
2014 | Conference paper
Source: Self-asserted source
Ponnuswamy Sadayappan

On characterizing the data movement complexity of computational DAGs for parallel execution

26th ACM Symposium on Parallelism in Algorithms and Architectures, SPAA '14, Prague, Czech Republic - June 23 - 25, 2014
2014 | Conference paper
DOI: 10.1145/2612669.2612694
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

On Using the Roofline Model with Lower Bounds on Data Movement

TACO
2014 | Journal article
DOI: 10.1145/2693656
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

The Relation Between Diamond Tiling and Hexagonal Tiling

Parallel Process. Lett.
2014 | Journal article
DOI: 10.1142/S0129626414410023
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

A stencil compiler for short-vector SIMD architectures

International Conference on Supercomputing, ICS'13, Eugene, OR, USA - June 10 - 14, 2013
2013 | Conference paper
DOI: 10.1145/2464996.2467268
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

Polyhedral-based data reuse optimization for configurable computing

The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013
2013 | Conference paper
DOI: 10.1145/2435264.2435273
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

When polyhedral transformations meet SIMD code generation

ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '13, Seattle, WA, USA, June 16-19, 2013
2013 | Conference paper
DOI: 10.1145/2491956.2462187
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 2)‎

Automatic C-to-CUDA Code Generation for Affine Programs

Compiler Construction, 19th International Conference, CC 2010, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2010, Paphos, Cyprus, March 20-28, 2010. Proceedings
2010 | Conference paper
DOI: 10.1007/978-3-642-11970-5\_14
Source: Self-asserted source
Ponnuswamy Sadayappan

DynTile: Parametric tiled loop generation for parallel execution on multicore processors

24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Conference Proceedings
2010 | Conference paper
DOI: 10.1109/IPDPS.2010.5470459
Source: Self-asserted source
Ponnuswamy Sadayappan

Parameterized tiling revisited

Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010
2010 | Conference paper
DOI: 10.1145/1772954.1772983
Source: Self-asserted source
Ponnuswamy Sadayappan

Parametric multi-level tiling of imperfectly nested loops

Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009
2009 | Conference paper
DOI: 10.1145/1542275.1542301
Source: Self-asserted source
Ponnuswamy Sadayappan

A compiler framework for optimization of affine loop nests for gpgpus

Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008
2008 | Conference paper
DOI: 10.1145/1375527.1375562
Source: Self-asserted source
Ponnuswamy Sadayappan

A practical automatic polyhedral parallelizer and locality optimizer

Proceedings of the ACM SIGPLAN 2008 Conference on Programming Language Design and Implementation, Tucson, AZ, USA, June 7-13, 2008
2008 | Conference paper
DOI: 10.1145/1375581.1375595
Source: Self-asserted source
Ponnuswamy Sadayappan
grade
Preferred source (of 4)‎

Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2008, Salt Lake City, UT, USA, February 20-23, 2008
2008 | Conference paper
DOI: 10.1145/1345206.1345210
Source: Self-asserted source
Ponnuswamy Sadayappan

Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model

Compiler Construction, 17th International Conference, CC 2008, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2008, Budapest, Hungary, March 29 - April 6, 2008. Proceedings
2008 | Conference paper
DOI: 10.1007/978-3-540-78791-4\_9
Source: Self-asserted source
Ponnuswamy Sadayappan
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