Personal information

FPGAs, partial reconfiguration, SoC, computer architecture
Peru

Biography

Aurelio Morales Villanueva was born in Lima, Perú in 1961. He received his Bachelor of Science degree and the Master of Science degree in electronics engineering from the Universidad Nacional de Ingeniería (UNI) in Lima, in 1985, and 1991, respectively. He received a Fulbright Fellowship in 1992 and enrolled in a M.S. program at State University of New York, Buffalo, and earned the M.S. degree in electrical engineering in 1994. Back to Perú, he joined UNI as a part time associate professor while working at Telefónica del Perú.
Aurelio enrolled in the Ph.D. program in the Department of Electrical and Computer Engineering at the University of Florida in the fall of 2009, as a recipient of the Unidad Coordinadora del Programa de Ciencia y Tecnología (FINCyT) Fellowship, and went on a leave of absence at UNI. While pursuing his degree, Aurelio participated as a research volunteer in the NSF Center for High-Performance Reconfigurable Computing (CHREC).
He received his Ph.D. from the University of Florida in the summer of 2015 and went back to Perú, where he is currently a tenure-track full time professor of the College of Electrical and Electronics Engineering at UNI. His current research interests include FPGA dynamic partial reconfiguration, computer architecture, reconfigurable computing, and embedded systems.

Activities

Employment (3)

Universidad Nacional de Ingeniería: Rimac, Lima, PE

2012-06-01 to present | Professor (Facultad de Ingeniería Eléctrica y Electrónica)
Employment
Source: Self-asserted source
Aurelio Morales-Villanueva

Universidad Nacional de Ingeniería: Rimac, Lima, PE

1994-04-01 to 2012-05-31 | Associate Professor (Facultad de Ingeniería Eléctrica y Electrónica)
Employment
Source: Self-asserted source
Aurelio Morales-Villanueva

Universidad Nacional de Ingeniería: Rimac, Lima, PE

1989-05-01 to 1992-09-30 | Assistant Professor (Facultad de Ingeniería Eléctrica y Electrónica)
Employment
Source: Self-asserted source
Aurelio Morales-Villanueva

Education and qualifications (5)

Consejo Nacional de Ciencia y Tecnología e Innovación Tecnológica: Lima, PE

2022-06-17 to present | Investigador RENACYT (Nivel VII)
Qualification
CÓDIGO RENACYT: P0010626
Source: check_circle
CONCYTEC
grade
Preferred source (of 2)‎

University of Florida: Gainesville, FL, US

2009-08-24 to 2015-08-07 | Doctor of Phylosophy (Electrical and Computer Engineering)
Education
Source: Self-asserted source
Aurelio Morales-Villanueva

University at Buffalo - The State University of New York: Buffalo, NY, US

1992-08-15 to 1993-12-15 | Master of Science (Electrical Engineering)
Education
Source: Self-asserted source
Aurelio Morales-Villanueva

Universidad Nacional de Ingeniería: Lima, Lima, PE

1985-08-01 to 1987-12-15 | Master of Science (Electrical and Electronics)
Education
Source: Self-asserted source
Aurelio Morales-Villanueva

Universidad Nacional de Ingeniería: Lima, Lima, PE

1979-11-01 to 1984-12-15 | Bachelor of Science (Electrical and Electronics)
Education
Source: Self-asserted source
Aurelio Morales-Villanueva

Professional activities (2)

Institute of Electrical and Electronics Engineers: Piscataway, New Jersey, US

2009-09-01 to present | Member
Membership
Source: Self-asserted source
Aurelio Morales-Villanueva

Colegio de Ingenieros de Perú: Lima, Lima, PE

1990-07-02 to present | Member
Membership
Source: Self-asserted source
Aurelio Morales-Villanueva

Works (8)

Uncertainty Evaluation of a Gas Turbine Model Based on a Nonlinear Autoregressive Exogenous Model and Monte Carlo Dropout

Sensors
2024-01-12 | Journal article
Contributors: Armando Cajahuaringa; Rubén Aquize Palacios; Juan M. Mauricio Villanueva; Aurelio Morales-Villanueva; José Machuca; Juan Contreras; Kiara Rodríguez Bautista
Source: check_circle
Crossref
grade
Preferred source (of 2)‎

Exploring Dynamic Partial Reconfiguration in a Tightly-coupled Coprocessor Attached to a RISC-V Soft-processor on a FPGA

2021 IEEE XXVIII International Conference on Electronics, Electrical Engineering and Computing (INTERCON)
2021-08-05 | Conference paper
Source: Self-asserted source
Aurelio Morales-Villanueva

Relocation of hardware tasks across networked partially reconfigurable FPGAs

Source: Self-asserted source
Aurelio Morales-Villanueva

Configuration prefetching and reuse for preemptive hardware multitasking on partially reconfigurable FPGAs

Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
2016 | Conference paper
EID:

2-s2.0-84973662092

Contributors: Morales-Villanueva, A.; Kumar, R.; Gordon-Ross, A.
Source: Self-asserted source
Aurelio Morales-Villanueva via Scopus - Elsevier

Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs

Proceedings - 2015 IEEE 29th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2015
2015 | Conference paper
EID:

2-s2.0-84962321387

Contributors: Morales-Villanueva, A.; Gordon-Ross, A.
Source: Self-asserted source
Aurelio Morales-Villanueva via Scopus - Elsevier

HTR: On-chip hardware task relocation for partially reconfigurable FPGAs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2013 | Book
EID:

2-s2.0-84875489409

Contributors: Morales-Villanueva, A.; Gordon-Ross, A.
Source: Self-asserted source
Aurelio Morales-Villanueva via Scopus - Elsevier
grade
Preferred source (of 2)‎

On-chip context save and restore of hardware tasks on partially reconfigurable FPGAS

Proceedings - 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2013
2013 | Conference paper
EID:

2-s2.0-84881147642

Contributors: Morales-Villanueva, A.; Gordon-Ross, A.
Source: Self-asserted source
Aurelio Morales-Villanueva via Scopus - Elsevier
grade
Preferred source (of 2)‎

Design and implementation of a neural network in an FPGA for pattern recovery

TECNIA
2007-12-01 | Journal article
Contributors: Aurelio Morales Villanueva; Cesar Briceño Aranda
Source: check_circle
Crossref