Personal information

Websites & social links

Koibuchi Lab, National Institute of Informatics, NII

Other IDs

Researcher Name Resolver ID: 1000040413926

Keywords

Interconnection networks, computer architecture, high-performance computing, optical networks

Countries

Japan

Biography

Michihiro Koibuchi received the PhD degree from Keio University, Yokohama, Kanagawa, Japan, in 2003. He is currently an Associate Professor at the National Institute of Informatics, and SOKENDAI, Tokyo, Japan. His research interests include the areas of high-performance computing and interconnection networks. He published over 100 referred technical conference and journal papers (9 in IEEE Trans. on Parallel and Distributed Systems, 5 in IPDPS, 4 in HPCA, and 3 in IEEE Trans. on Computers). He is a senior member of the IEEE, the IEEE Computer Society, IPSJ, and IEICE.

Activities

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Employment (1)

National Institute of Informatics: Chiyoda, Tokyo, JP

Associate Professor
Employment
Source: Self-asserted source
Michihiro Koibuchi

Works (5)

OPTWEB: A Lightweight Fully Connected Inter-FPGA Network for Efficient Collectives

IEEE Transactions on Computers
2021-06-01 | Journal article
DOI: 10.1109/tc.2021.3068715
Part of ISSN: 0018-9340
Part of ISSN: 1557-9956
Part of ISSN: 2326-3814
Source: Self-asserted source
Michihiro Koibuchi

The Case for Water-Immersion Computer Boards

Proceedings of the 48th International Conference on Parallel Processing
2019-08-05 | Conference paper
DOI: 10.1145/3337821.3337830
Source: Self-asserted source
Michihiro Koibuchi

A case for random shortcut topologies for HPC interconnects

ACM SIGARCH Computer Architecture News
2012-09-05 | Journal article
DOI: 10.1145/2366231.2337179
Part of ISSN: 0163-5964
Source: Self-asserted source
Michihiro Koibuchi

Prediction router: Yet another low latency on-chip router architecture

2009 IEEE 15th International Symposium on High Performance Computer Architecture
2009-02 | Conference paper
DOI: 10.1109/hpca.2009.4798274
Source: Self-asserted source
Michihiro Koibuchi

A Lightweight Fault-Tolerant Mechanism for Network-on-Chip

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
2008-04 | Conference paper
DOI: 10.1109/nocs.2008.4492721
Source: Self-asserted source
Michihiro Koibuchi

Peer review (2 reviews for 1 publication/grant)

Review activity for Future generation computer systems. (2)
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