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Works (50 of 77)

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Page 1 of 2

Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors

IEEE Access
2025 | Journal article
DOI: 10.1109/ACCESS.2025.3527028
Contributors: Mael Tourres; Cyrille Chavet; Bertrand Le Gal; Philippe Coussy
Source: check_circle
Crossref

Next Generation 3-gamma PET with Xenon Liquid Camera using a High-Throughput Hardware Event-Builder Architecture

2024-12-27 | Preprint
DOI: 10.36227/techrxiv.173532318.88293356/v1
Contributors: Cyrille Chavet; C Davril; A Seraj; G Demazet
Source: check_circle
Crossref

Back-to-Back Butterfly Network: an Adaptive Permutation Network for New Communication Standards

Journal of Signal Processing Systems
2021-01-23 | Journal article
DOI: 10.1007/s11265-020-01628-w
URI: hal-03119275
Contributors: Hassan Harb; Cyrille Chavet
Source: Self-asserted source
Cyrille Chavet via HAL
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Fully Parallel Circular-Shift Rotation Network for Communication Standards

IEEE Transactions on Circuits and Systems II: Express Briefs
2020 | Journal article
DOI: 10.1109/TCSII.2020.2997691
URI: hal-02804289
Contributors: Hassan Harb; Cyrille Chavet
Source: Self-asserted source
Cyrille Chavet via HAL
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Toward Secured IoT Devices: a Shuffled 8-Bit AES Hardware Implementation

2020-10-12 | Conference paper
URI: hal-02511667
Contributors: Ghita Harcha; Vianney Lapotre; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards

2020-05-04 | Conference paper
HAL: hal-02493104
Contributors: Hassan Harb; Cyrille Chavet
Source: Self-asserted source
Cyrille Chavet via HAL

Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards

2020-05-04 | Conference paper
URI: hal-02493104
Contributors: Hassan Harb; Cyrille Chavet
Source: Self-asserted source
Cyrille Chavet via HAL

SOLVING MEMORY ACCESS CONFLICTS IN LTE-4G STANDARD

2019-05-27 | Conference paper
URI: hal-02060036
Contributors: Cyrille Chavet; F Lozachmeur; T Barguil; A Hussein; P Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Clone-Based Encoded Neural Networks to Design Efficient Associative Memories

IEEE Transactions on Neural Networks and Learning Systems
2019-01-14 | Journal article
DOI: 10.1109/TNNLS.2018.2890658
URI: hal-02060021
Contributors: Hugues Wouafo; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Efficient Scalable Hardware Architecture for Highly Performant Encoded Neural Networks

2017-10-02 | Conference paper
URI: hal-01565226
Contributors: Hugues Nono Wouafo; Cyrille Chavet; Robin Danilo; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

A Dynamically Reconfigurable ECC Decoder Architecture for the next generation communication standards (5G, SDR and behond)

2016-10-10 | Conference paper
HAL: hal-01344550
Contributors: Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

A Dynamically Reconfigurable ECC Decoder Architecture for the next generation communication standards (5G, SDR and behond)

2016-10-10 | Conference paper
URI: hal-01344550
Contributors: Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Associative memory based on clustered neural networks: improved model and architecture for oriented edge detection

2016-10-10 | Conference paper
URI: hal-01364943
Contributors: Robin Danilo; Hugues Nono Wouafo; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Amélioration des performances des mémoires associatives par les réseaux à clones

2016-06-08 | Conference paper
HAL: hal-01318028
Contributors: Hugues Nono; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

A Dynamically Reconfigurable ECC Decoder Architecture

2016-03-15 | Conference paper
URI: hal-01262057
Contributors: Cyrille Chavet; Philippe Coussy; Sani Awais Hussein
Source: Self-asserted source
Cyrille Chavet via HAL

Modèle et Architecture de Réseaux de Neurones Récurrents à Clones

2015-09-14 | Conference paper
HAL: hal-01167378
Contributors: Cyrille Chavet; Hugues Nono Wouafo; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Modèle et Architecture de Réseaux de Neurones Récurrents à Clones

2015-09-14 | Conference paper
HAL: hal-01291218
Contributors: Hugues Nono Wouafo; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Improving Storage of Patterns in Recurrent Neural Networks: Clone-Based Model and Architecture

2015-05-25 | Conference paper
URI: hal-01167364
Contributors: Cyrille Chavet; Hugues Nono Wouafo; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Improving Storage of Patterns in Recurrent Neural Networks: Clones Based Model and Architecture

2015-05-25 | Conference paper
URI: hal-01101580
Contributors: Hugues Nono Wouafo; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Improving storage of patterns in recurrent neural networks: Clone-based model and architecture

2015-05-24 | Conference paper
DOI: 10.1109/ISCAS.2015.7168699
URI: hal-02511108
Contributors: Hugues Wouafo; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories

ACM Journal on Emerging Technologies in Computing Systems
2015-04-27 | Journal article
DOI: 10.1145/2629510
URI: hal-02511077
Contributors: Philippe Coussy; Cyrille Chavet; Hugues Nono Wouafo; Laura Conde-Canencia
Source: Self-asserted source
Cyrille Chavet via HAL

Improving Storage of Patterns in Binary Cluster-Based Neural Networks: Clone-based Model and Architecture

2015-03-13 | Conference paper
HAL: hal-01101583
Contributors: Hugues Nono Wouafo; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

In-place memory mapping approach for optimized parallel hardware interleaver architectures

2015-03-09 | Conference paper
URI: hal-01101586
Contributors: Saeed Ur Reehman; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

In-Place Memory Mapping Approach for Optimized Parallel Hardware Interleaver Architectures

2015-03-09 | Conference paper
DOI: 10.7873/DATE.2015.1055
HAL: hal-02511081
Contributors: Saeed Ur Reehman; Cyrille Chavet; Philippe Coussy; Awais Sani
Source: Self-asserted source
Cyrille Chavet via HAL

A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code

2014-12-08 | Conference paper
URI: hal-01069265
Contributors: Mickael Lanoe; Bordin Matteo; Dominique Heller; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code

2014-12-08 | Book
URI: hal-01075807
Contributors: Bordin Matteo; Mickael Lanoe; Dominique Heller; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Hardware design of parallel interleaver architecture: a survey

2014-11-10 | Book chapter
HAL: hal-01009476
Contributors: Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Hardware design of parallel interleaver architecture: a survey

2014-11-10 | Book chapter
URI: hal-01009476
Contributors: Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Advanced Hardware Design for Error Correcting Codes

2014-11-03 | Book
URI: hal-01009474
Contributors: Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Advanced Hardware Design for Error Correcting Codes

2014-11-03 | Book
HAL: hal-01009474
Contributors: Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Modélisation de la vision inspirée du vivant

2014-10-30 | Conference paper
HAL: hal-01079094
Contributors: Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Modélisation de la vision inspirée du vivant

2014-10-30 | Conference paper
HAL: hal-01079098
Contributors: Philippe Coussy; Cyrille Chavet
Source: Self-asserted source
Cyrille Chavet via HAL

Modélisation de la vision inspirée du vivant

2014-10-30 | Conference paper
URI: hal-01079094
Contributors: Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Fully-Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories

ACM Journal on Emerging Technologies in Computing Systems
2014-09-15 | Journal article
URI: hal-01009473
Contributors: Philippe Coussy; Cyrille Chavet; Laura Conde Canencia; Hugues Nono Wouafo
Source: Self-asserted source
Cyrille Chavet via HAL

Designing optimized parallel interleaver architecture through network customization

2014-06-10 | Conference paper
HAL: hal-01009679
Contributors: Cyrille Chavet; Philippe Coussy; Saeed Ur Reehman
Source: Self-asserted source
Cyrille Chavet via HAL

Architecture de réseau de neurone, procédé d'obtention et programmes correspondants

2014-06-02 | Patent
URI: hal-00776062
Contributors: Cyrille Chavet; Philippe Coussy; Nicolas Charpentier
Source: Self-asserted source
Cyrille Chavet via HAL

A Memory Mapping Approach based on Network Customization to Design Conflict-Free Parallel Hardware Architectures

2014-05-14 | Conference paper
URI: hal-01009477
Contributors: Cyrille Chavet; Philippe Coussy; Saeed Ur Reehman
Source: Self-asserted source
Cyrille Chavet via HAL

Embedding Polynomial Time Memory Mapping and Routing Algorithms on-chip to Design Configurable Decoder Architecture

2014-05-08 | Conference paper
URI: hal-01009478
Contributors: Saeed Ur Reehman; Awais Hussein Sani; Philippe Coussy; Cyrille Chavet
Source: Self-asserted source
Cyrille Chavet via HAL

VLSI Architectures and NoCs for Neural Coding

2014-03-17 | Conference paper
HAL: hal-01009489
Contributors: Jean-Philippe Diguet; Philippe Coussy; Cyrille Chavet
Source: Self-asserted source
Cyrille Chavet via HAL

VLSI Architectures and NoCs for Neural Coding

2014-03-17 | Conference paper
URI: hal-01009489
Contributors: Jean-Philippe Diguet; Philippe Coussy; Cyrille Chavet
Source: Self-asserted source
Cyrille Chavet via HAL

A CONFLICT-FREE MEMORY MAPPING APPROACH TO DESIGN PARALLEL HARDWARE INTERLEAVER ARCHITECTURES WITH OPTIMIZED NETWORK AND CONTROLLER

2013-10-15 | Conference paper
HAL: hal-00861312
Contributors: Aroua Briki; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

A CONFLICT-FREE MEMORY MAPPING APPROACH TO DESIGN PARALLEL HARDWARE INTERLEAVER ARCHITECTURES WITH OPTIMIZED NETWORK AND CONTROLLER

2013-10-15 | Conference paper
URI: hal-00861312
Contributors: Aroua Briki; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Dynamic Branch Prediction For High-Level Synthesis

2013-09-04 | Conference paper
URI: hal-00830417
Contributors: Vianney Lapotre; Philippe Coussy; Cyrille Chavet; Hugues Nono Wouafo; Robin Danilo
Source: Self-asserted source
Cyrille Chavet via HAL

Introduction de la prédiction de branchement dans la synthèse de haut niveau

Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques
2013-09-02 | Journal article
HAL: hal-00799808
Contributors: Vianney Lapotre; Philippe Coussy; Cyrille Chavet
Source: Self-asserted source
Cyrille Chavet via HAL

A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm

IEEE Transactions on Signal Processing
2013-06-07 | Journal article
URI: hal-00820779
Contributors: Awais Hussein Sani; Saeed Ur Reehman; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

ON-CHIP IMPLEMENTATION OF MEMORY MAPPING ALGORITHM TO SUPPORT FLEXIBLE DECODER ARCHITECTURE

2013-05-27 | Conference paper
URI: hal-00799771
Contributors: Sani Awais Hussein; Saeed Ur Reehman; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

A Memory Mapping Approach for Network and Controller Optimization in Parallel Interleaver Architectures

2013-05-02 | Conference paper
URI: hal-00799762
Contributors: Aroua Briki; Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Dispositif auto-configurable d'entrelacement/désentrelacement de trames de données

2013-02-25 | Patent
HAL: hal-00749589
Contributors: Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Dispositif auto-configurable d'entrelacement/désentrelacement de trames de données

2013-02-25 | Patent
URI: hal-00749589
Contributors: Cyrille Chavet; Philippe Coussy
Source: Self-asserted source
Cyrille Chavet via HAL

Dedicated approach to explore design space for hardware architecture of turbo decoders

2012-10-17 | Conference paper
URI: hal-00721379
Contributors: Oscar Sanchez; Sani Awais Hussein; Saeed Ur Reehman; Cyrille Chavet; Philippe Coussy; Michel Jezequel; Christophe Jego
Source: Self-asserted source
Cyrille Chavet via HAL
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