Personal information

Biography

Dr. Loïc Siéler, Associate Professor at the University of Lorraine, UFR Sciences Fondamentales et Appliquées - Metz (France). He received the PhD. Degree in "Robotic Vision System" from Blaise Pascal University of Clermont-Ferrand, France, in december 2011. He worked on the problematic of Multi-Processor SoC architecture dedicated to vision system at (LASMEA) "Laboratoire des Sciences et Matériaux pour l'Electronique, et d'Automatique". He joined the "Conception Optimisation and Modelisation des Systems Laboratory" (LCOMS) in septembre 2012, as permanent member of "Architectures des Systèmes EMbarqués et Capteurs inteligents" (ASEC) team. His research interests are the FPGA design of dedicated and adaptative architectures to address the problem of computing time which are common in: transmission, computing vision and data processing.

Activities

Employment (1)

Université de Lorraine: Metz, Lorraine, FR

2012-09-01 to present | Maître de conférences (UFR SciFa)
Employment
Source: Self-asserted source
Loïc Siéler

Works (13)

A Modified Algorithm for QRS Complex Detection for FPGA Implementation

Circuits, Systems, and Signal Processing
2018-07 | Journal article
Part of ISSN: 0278-081X
Part of ISSN: 1531-5878
Source: Self-asserted source
Loïc Siéler

Asymmetric optical cryptosystem for color image based on equal modulus decomposition in gyrator transform domains

Optics and Lasers in Engineering
2017 | Journal article
EID:

2-s2.0-85009382340

Contributors: Chen, H.; Tanougast, C.; Liu, Z.; Sieler, L.
Source: Self-asserted source
Loïc Siéler via Scopus - Elsevier

Stress Recognition from Heterogeneous Datav

2016-12 | Journal article
Source: Self-asserted source
Loïc Siéler

Configurable and high-throughput architectures for Quasi-cyclic low-density parity-check codes

2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014
2015 | Conference paper
EID:

2-s2.0-84925424813

Contributors: Al Hariri, A.A.; Monteiro, F.; Siéler, L.; Dandache, A.
Source: Self-asserted source
Loïc Siéler via Scopus - Elsevier

A high throughput configurable partially-parallel decoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes

Proceedings of the 2014 29th Conference on Design of Circuits and Integrated Systems, DCIS 2014
2014 | Conference paper
EID:

2-s2.0-84938117702

Contributors: Hariri, A.A.A.; Monteiro, F.; Sieler, L.; Dandache, A.
Source: Self-asserted source
Loïc Siéler via Scopus - Elsevier

A Li-Ion cell testbench for fast characterization and modeling

Proceedings - 2014 International Conference on Control, Decision and Information Technologies, CoDIT 2014
2014 | Conference paper
EID:

2-s2.0-84921367737

Contributors: Cicero, L.; Tanougast, C.; Ramenah, H.; Sieler, L.; Lecerf, F.
Source: Self-asserted source
Loïc Siéler via Scopus - Elsevier

A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013
2013 | Conference paper
EID:

2-s2.0-84885226695

Contributors: Al Hariri, A.A.; Monteiro, F.; Sieler, L.; Dandache, A.
Source: Self-asserted source
Loïc Siéler via Scopus - Elsevier

VHDL-AMS electro-thermal modeling of a lithium-ion battery

2013 25th International Conference on Microelectronics, ICM 2013
2013 | Conference paper
EID:

2-s2.0-84896753098

Contributors: Machado, H.; Cicero, L.; Tanougast, C.; Ramenah, H.; Sieler, L.; Jean, P.; Milhas, P.; Dandache, A.
Source: Self-asserted source
Loïc Siéler via Scopus - Elsevier

A generic packet router IP for multi-processors network-on-chip

8th FPGAworld Conference - Academic Proceedings 2011, FPGAworld 2011
2011 | Conference paper
EID:

2-s2.0-84858742336

Contributors: Siéler, L.; Damez, L.; Ballet, B.; Landrault, A.; Dérutin, J.-P.
Source: Self-asserted source
Loïc Siéler via Scopus - Elsevier

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

Journal of Real-Time Image Processing
2011 | Journal article
EID:

2-s2.0-79951581038

Contributors: Damez, L.; Sieler, L.; Landrault, A.; Dérutin, J.P.
Source: Self-asserted source
Loïc Siéler via Scopus - Elsevier

A generic MP-SoC design methodology for the fast prototyping of embedded image processing

Proceedings of the International Conference on Microelectronics, ICM
2010 | Conference paper
EID:

2-s2.0-79951709386

Contributors: Siéler, L.; Dérutin, J.P.; Damez, L.; Landrault, A.
Source: Self-asserted source
Loïc Siéler via Scopus - Elsevier

A MP-SoC design methodology for the fast prototyping of embedded image processing system

2010 International SoC Design Conference, ISOCC 2010
2010 | Conference paper
EID:

2-s2.0-79851502095

Contributors: Siéler, L.; Dérutin, J.P.; Landrault, A.
Source: Self-asserted source
Loïc Siéler via Scopus - Elsevier

A scalable and embedded FPGA architecture for efficient computation of grey level co-occurrence matrices and Haralick textures features

Microprocessors and Microsystems
2010 | Journal article
EID:

2-s2.0-73149105101

Contributors: Siéler, L.; Tanougast, C.; Bouridane, A.
Source: Self-asserted source
Loïc Siéler via Scopus - Elsevier