Personal information

Activities

Employment (3)

Imec: Leuven, BE

2019-11-01 to present | Program Manager (Logic Technologies)
Employment
Source: Self-asserted source
Eugenio Dentoni Litta

Imec: Leuven, BE

2016-02-01 to 2019-11-01 | R&D Integration Engineer (Semiconductor Technologies and Systems)
Employment
Source: Self-asserted source
Eugenio Dentoni Litta

KTH Royal Institute of Technology: Stockholm, SE

2014-07-01 to 2015-12-31 | Researcher (Dept. of Integrated Devices and Circuits)
Employment
Source: Self-asserted source
Eugenio Dentoni Litta

Education and qualifications (3)

KTH Royal Institute of Technology: Stockholm, SE

2010 to 2014 | Ph.D. in Information and Communication Technology / Micro- and Nanoelectronics
Education
Source: Self-asserted source
Eugenio Dentoni Litta

Università degli Studi di Salerno: Salerno, IT

2007 to 2010 | M.Sc. in Electronics Engineering
Education
Source: Self-asserted source
Eugenio Dentoni Litta

Università degli Studi di Salerno: Salerno, IT

2004 to 2007 | B.Sc. in Electronics Engineering
Education
Source: Self-asserted source
Eugenio Dentoni Litta

Works (50 of 64)

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Page 1 of 2

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery

IEEE International Reliability Physics Symposium Proceedings
2022 | Conference paper
EID:

2-s2.0-85130738080

Part of ISSN: 15417026
Contributors: Bastos, J.P.; O'Sullivan, B.J.; Franco, J.; Tyaginov, S.; Truijen, B.; Chasin, A.; Degraeve, R.; Kaczer, B.; Ritzenthaler, R.; Capogreco, E. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications

Japanese Journal of Applied Physics
2021 | Journal article
EID:

2-s2.0-85103820181

Part of ISSN: 13474065 00214922
Contributors: Spessot, A.; Ritzenthaler, R.; Litta, E.D.; Dupuy, E.; O'Sullivan, B.; Bastos, J.; Capogreco, E.; Miyaguchi, K.; MacHkaoutsan, V.; Yoon, Y. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Buried Power Rail Metal exploration towards the 1 nm Node

Technical Digest - International Electron Devices Meeting, IEDM
2021 | Conference paper
EID:

2-s2.0-85126967741

Part of ISSN: 01631918
Contributors: Gupta, A.; Radisic, D.; Maes, J.W.; Pedreira, O.V.; Soulie, J.-P.; Jourdan, N.; Mertens, H.; Bandyopadhyay, S.; Le, Q.T.; Pacco, A. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and beyond

Technical Digest - International Electron Devices Meeting, IEDM
2021 | Conference paper
EID:

2-s2.0-85126942418

Part of ISSN: 01631918
Contributors: Ritzenthaler, R.; Mertens, H.; Eneman, G.; Simoen, E.; Bury, E.; Eyben, P.; Bufler, F.M.; Oniki, Y.; Briggs, B.; Chan, B.T. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices

Technical Digest - International Electron Devices Meeting, IEDM
2021 | Conference paper
EID:

2-s2.0-85126915630

Part of ISSN: 01631918
Contributors: Arimura, H.; Ragnarsson, L.-A.; Oniki, Y.; Franco, J.; Vandooren, A.; Brus, S.; Leonhardt, A.; Sippola, P.; Ivanova, T.; Alessio Verni, G.A. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster

Digest of Technical Papers - Symposium on VLSI Technology
2021 | Conference paper
EID:

2-s2.0-85123684356

Part of ISSN: 07431562
Contributors: Veloso, A.; Jourdain, A.; Hiblot, G.; Schleicher, F.; D'Have, K.; Sebaai, F.; Radisic, D.; Loo, R.; Hopf, T.; De Keersgieter, A. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space

Digest of Technical Papers - Symposium on VLSI Technology
2021 | Conference paper
EID:

2-s2.0-85117817039

Part of ISSN: 07431562
Contributors: Mertens, H.; Ritzenthaler, R.; Oniki, Y.; Briggs, B.; Chan, B.T.; Hikavyy, A.; Hopf, T.; Mannaert, G.; Tao, Z.; Sebaai, F. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Low Temperature Atomic Hydrogen Treatment for Superior NBTI Reliability-Demonstration and Modeling across SiO<sub>2</sub> IL Thicknesses from 1.8 to 0.6 nm for I/O and Core Logic

Digest of Technical Papers - Symposium on VLSI Technology
2021 | Conference paper
EID:

2-s2.0-85123639472

Part of ISSN: 07431562
Contributors: Franco, J.; de Marneffe, J.-F.; Vandooren, A.; Arimura, H.; Ragnarsson, L.-Å.; Claes, D.; Litta, E.D.; Horiguchi, N.; Croes, K.; Linten, D. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Low-Temperature atomic and molecular hydrogen anneals for enhanced chemical bf{SiO}_{2} IL quality in low thermal budget RMG stacks

Technical Digest - International Electron Devices Meeting, IEDM
2021 | Conference paper
EID:

2-s2.0-85126983143

Part of ISSN: 01631918
Contributors: Franco, J.; Arimura, H.; De Marneffe, J.-F.; Wu, Z.; Vandooren, A.; Ragnarsson, L.-A.; Litta, E.D.; Horiguchi, N.; Croes, K.; Linten, D. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Challenges and Solutions of Replacement Metal Gate Patterning to Enable Gate-all-Around Device Scaling

Solid State Phenomena
2021-02 | Journal article
Part of ISSN: 1662-9779
Contributors: Yusuke Oniki; Lars Åke Ragnarsson; Hideaki Iino; Daire Cott; Boon Teik Chan; Farid Sebaai; Toby Hopf; Harold Dekkers; Eugenio Dentoni Litta; Efrain Altamirano Sánchez et al.
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Buried Power Rail Integration with FinFETs for Ultimate CMOS Scaling

IEEE Transactions on Electron Devices
2020 | Journal article
EID:

2-s2.0-85097335278

Part of ISSN: 15579646 00189383
Contributors: Gupta, A.; Pedreira, O.V.; Arutchelvan, G.; Zahedmanesh, H.; Devriendt, K.; Mertens, H.; Tao, Z.; Ritzenthaler, R.; Wang, S.; Radisic, D. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

Digest of Technical Papers - Symposium on VLSI Technology
2020 | Conference paper
EID:

2-s2.0-85098121767

Part of ISSN: 07431562
Contributors: Gupta, A.; Mertens, H.; Tao, Z.; Demuynck, S.; Bommels, J.; Arutchelvan, G.; Devriendt, K.; Pedreira, O.V.; Ritzenthaler, R.; Wang, S. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Buried power rail scaling and metal assessment for the 3 nm node and beyond

Technical Digest - International Electron Devices Meeting, IEDM
2020 | Conference paper
EID:

2-s2.0-85102923702

Part of ISSN: 01631918
Contributors: Gupta, A.; Pedreira, O.V.; Tao, Z.; Mertens, H.; Radisic, D.; Jourdan, N.; Devriendt, K.; Heylen, N.; Wang, S.; Chehab, B. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Buried power SRAM DTCO and system-level benchmarking in N3

Digest of Technical Papers - Symposium on VLSI Technology
2020 | Conference paper
EID:

2-s2.0-85094889680

Part of ISSN: 07431562
Contributors: Salahuddin, S.; Perumkunnil, M.; Litta, E.D.; Gupta, A.; Weckx, P.; Ryckaert, J.; Na, M.-H.; Spessot, A.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

Digest of Technical Papers - Symposium on VLSI Technology
2020 | Conference paper
EID:

2-s2.0-85097340794

Part of ISSN: 07431562
Contributors: Subramanian, S.; Hosseini, M.; Chiarella, T.; Sarkar, S.; Schuddinck, P.; Chan, B.T.; Radisic, D.; Mannaert, G.; Hikavyy, A.; Rosseel, E. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability

IEEE Transactions on Device and Materials Reliability
2020 | Journal article
EID:

2-s2.0-85083017660

Part of ISSN: 15582574 15304388
Contributors: Boubaaya, M.; O'Sullivan, B.J.; Djezzar, B.; Franco, J.; Litta, E.D.; Ritzenthaler, R.; Dupuy, E.; MacHkaoutsan, V.; Fazan, P.; Kim, C. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

IEEE Transactions on Electron Devices
2020 | Journal article
EID:

2-s2.0-85097342163

Part of ISSN: 15579646 00189383
Contributors: Vincent, B.; Hathwar, R.; Kamon, M.; Ervin, J.; Schram, T.; Chiarella, T.; Demuynck, S.; Baudot, S.; Siew, Y.K.; Kubicek, S. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation

IEEE International Reliability Physics Symposium Proceedings
2020 | Conference paper
EID:

2-s2.0-85088380733

Part of ISSN: 15417026
Contributors: Chasin, A.; Franco, J.; Bury, E.; Ritzenthaler, R.; Litta, E.; Spessot, A.; Horiguchi, N.; Linten, D.; Kaczer, B.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology

IEEE Transactions on Electron Devices
2020-11 | Journal article
Contributors: Shairfe Muhammad Salahuddin; Eugenio Dentoni Litta; Anshul Gupta; Romain Ritzenthaler; Marc Schaekers; Jean-Luc Everaert; Hao Yu; Anne Vandooren; Julien Ryckaert; Myung-Hee Na et al.
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Overview of Bias Temperature Instability in Scaled DRAM Logic for Memory Transistors

IEEE Transactions on Device and Materials Reliability
2020-06 | Journal article
Part of ISSN: 1530-4388
Contributors: B. J. O'Sullivan; R. Ritzenthaler; E. Dentoni Litta; E. Simoen; V. Machkaoutsan; P. Fazan; Y.-H. Ji; C. Kim; A. Spessot; D. Linten et al.
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Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High/Metal Gate Devices

IEEE International Reliability Physics Symposium Proceedings
2019 | Conference paper
EID:

2-s2.0-85066750431

Part of ISSN: 15417026
Contributors: O'Sullivan, B.J.; Ritzenthaler, R.; Rzepa, G.; Wu, Z.; Litta, E.D.; Richard, O.; Conard, T.; Machkaoutsan, V.; Fazan, P.; Kim, C. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Novel forksheet device architecture as ultimate logic scaling device towards 2nm

Technical Digest - International Electron Devices Meeting, IEDM
2019 | Conference paper
EID:

2-s2.0-85081046631

Part of ISSN: 01631918
Contributors: Weckx, P.; Gupta, M.; Oniki, Y.; Ragnarsson, L.-A.; Horiguchi, N.; Spessot, A.; Verkest, D.; Ryckaert, J.; Litta, E.D.; Yakimets, D. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

Can we optimize the gate oxide quality of DRAM input/output pMOSFETs by a post-deposition treatment?

Semiconductor Science and Technology
2018 | Journal article
Part of ISSN: 0268-1242
Contributors: E Simoen; B O’Sullivan; R Ritzenthaler; E Dentoni-Litta; T Schram; N Horiguchi; C Claeys
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First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs

IEEE Transactions on Electron Devices
2018 | Journal article
EID:

2-s2.0-85054655529

Part of ISSN: 00189383
Contributors: Capogreco, E.; Witters, L.; Arimura, H.; Sebaai, F.; Porret, C.; Hikavyy, A.; Loo, R.; Milenin, A.P.; Eneman, G.; Favia, P. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

Digest of Technical Papers - Symposium on VLSI Technology
2018 | Conference paper
EID:

2-s2.0-85055390398

Part of ISSN: 07431562
Contributors: Capogreco, E.; Witters, L.; Arimura, H.; Sebaai, F.; Porret, C.; Hikavyy, A.; Loo, R.; Milenin, A.P.; Eneman, G.; Favia, P. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

TaN Versus TiN Metal Gate Input/Output pMOSFETs: A Low-Frequency Noise Perspective

IEEE Transactions on Electron Devices
2018 | Journal article
Contributors: Eddy Simoen; Barry O'Sullivan; Romain Ritzenthaler; Eugenio Dentoni Litta; Tom Schram; Naoto Horiguchi; Cor Claeys
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Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

Technical Digest - International Electron Devices Meeting, IEDM
2018 | Conference paper
EID:

2-s2.0-85045201276

Part of ISSN: 01631918
Contributors: Mertens, H.; Ritzenthaler, R.; Pena, V.; Santoro, G.; Kenis, K.; Schulze, A.; Litta, E.D.; Chew, S.A.; Devriendt, K.; Chiarella, T. et al.
Source: Self-asserted source
Eugenio Dentoni Litta via Scopus - Elsevier

RMG Patterning by Digital Wet Etching of Polycrystalline Metal Films

Solid State Phenomena
2018-08 | Journal article
Part of ISSN: 1662-9779
Contributors: Yusuke Oniki; Guy Vereecke; Eugenio Dentoni Litta; Lars-Ake Ragnarsson; Harold Dekkers; Tom Schram; Frank Holsteyns; Naoto Horiguchi
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CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Japanese Journal of Applied Physics
2018-04-01 | Journal article
Contributors: Eugenio Dentoni Litta; Romain Ritzenthaler; Tom Schram; Alessio Spessot; Barry O’Sullivan; Vladimir Machkaoutsan; Pierre Fazan; Yunhyuck Ji; Geert Mannaert; Christophe Lorant et al.
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Treatments for reliability improvement in thick oxides diffusion and gate replacement I/O transistors

International Journal of Materials Engineering Innovation
2017 | Journal article
EID:

2-s2.0-85027582045

Part of ISSN: 17572762 17572754
Contributors: Ritzenthaler, R.; Cho, M.; Schram, T.; Spessot, A.; Simoen, E.; O'Sullivan, B.J.; Litta, E.D.; Horiguchi, N.
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Eugenio Dentoni Litta via Scopus - Elsevier

CMOS Integration of Thermally Stable Diffusion and Gate Replacement (D&amp;GR) High-k/Metal Gate Stacks in DRAM Periphery Transistors

Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials
2017-09 | Other
Contributors: E. Dentoni Litta; R. Ritzenthaler; T. Schram; A. Spessot; B. O'Sullivan; Y. Ji; G. Mannaert; C. Lorant; F. Sebaai; A. Thiam et al.
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Improving the low-frequency noise performance of input/output DRAM peripheral pMOSFETs

2017 International Conference on Noise and Fluctuations (ICNF)
2017-06 | Conference paper
Part of ISBN: 9781509027606
Contributors: E. Simoen; B.J. O'Sullivan; R. Ritzenthaler; E. Dentoni Litta; T. Schram; N. Horiguchi; V. Machkaoutsan; P. Fazan; Y. Li
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Gate stack engineering to enhance high-κ/metal gate reliability for DRAM I/O applications

2017 IEEE International Reliability Physics Symposium (IRPS)
2017-04 | Conference paper
Part of ISBN: 9781509066414
Contributors: B.J. O'Sullivan; R. Ritzenthaler; E. Simoen; E. Dentoni Litta; T. Schram; A. Chasin; D. Linten; N. Horiguchi; V Machkaoutsan; P Fazan et al.
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Three-Dimensional Integration of Ge and Two-Dimensional Materials for One-Dimensional Devices

Future Trends in Microelectronics
2016-09 | Other
Part of ISBN: 9781119069225
Contributors: M. Östling; E. Dentoni Litta; P.-E. Hellström
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(Invited) TmSiO as a CMOS-Compatible High-k Dielectric

ECS Transactions
2016-05 | Journal article
Part of ISSN: 1938-6737
Contributors: E. Dentoni Litta; P.-E. Hellstrom; M. Ostling
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(Invited) TmSiO As a CMOS-Compatible High-k Dielectric

ECS Meeting Abstracts
2016-04-01 | Journal article
Contributors: Eugenio Dentoni Litta; Per-Erik Hellström; Mikael Östling
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Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors

Nanoscale
2015 | Journal article
Contributors: S. Vaziri; M. Belete; E. Dentoni Litta; A. D. Smith; G. Lupina; M. C. Lemme; M. Östling
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Low-Frequency Noise Characterization of Ultra-Low Equivalent-Oxide-Thickness Thulium Silicate Interfacial Layer nMOSFETs

IEEE Electron Device Letters
2015 | Journal article
Part of ISSN: 0741-3106
Contributors: Maryam Olyaei; Eugenio Dentoni Litta; Per-Erik Hellstrom; Mikael Ostling; Bengt Gunnar Malm
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Enhanced Channel Mobility at Sub-nm EOT by Integration of a TmSiO Interfacial Layer in HfO<sub>2</sub>/TiN High-k/Metal Gate MOSFETs

IEEE J. Electron Devices Soc.
2015-09 | Journal article
Contributors: Eugenio Dentoni Litta; Per-Erik Hellstrom; Mikael Ostling
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Step tunneling-enhanced hot-electron injection in vertical graphene base transistors

2015 45th European Solid State Device Research Conference (ESSDERC)
2015-09 | Conference paper
Part of ISBN: 9781467371339
Contributors: S. Vaziri; M. Belete; A. D. Smith; E. Dentoni Litta; G. Lupina; M. C. Lemme; M. Ostling
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Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

Solid-State Electronics
2015-06 | Journal article
DOI:

10.1016/j.sse.2014.12.008

Contributors: E. Dentoni Litta; P.-E. Hellström; M. Östling
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Atomic-layer deposited thulium oxide as a passivation layer on germanium

J. Appl. Phys.
2015-06-07 | Journal article
Contributors: I. Z. Mitrovic; S. Hall; M. Althobaiti; D. Hesp; V. R. Dhanak; A. Santoni; A. D. Weerakkody; N. Sedghi; P. R. Chalker; C. Henkel et al.
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Characterization of high-k dielectrics using MeV elastic scattering of He ions

Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms
2015-03 | Journal article
DOI:

10.1016/j.nimb.2014.12.080

Contributors: C.J. Zoller; E. Dentoni Litta; D. Primetzhofer
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Integration of TmSiO/HfO<sub>2</sub> Dielectric Stack in Sub-nm EOT High-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula>/Metal Gate CMOS Technology

IEEE Trans. Electron Devices
2015-03 | Journal article
DOI:

10.1109/ted.2015.2391179

Contributors: Eugenio Dentoni Litta; Per-Erik Hellstrom; Mikael Ostling
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Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration

EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
2015-01 | Conference paper
DOI:

10.1109/ulis.2015.7063799

Contributors: K. Garidis; G. Jayakumar; A. Asadollahi; E. Dentoni Litta; P.-E. Hellstrom; M. Ostling
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Recent advances in high-k dielectrics and inter layer engineering

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
2014-10 | Conference paper
DOI:

10.1109/icsict.2014.7021327

Contributors: Mikael Ostling; Eugenio Dentoni Litta; Per-Erik Hellstrom
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Improved low-frequency noise for 0.3nm EOT thulium silicate interfacial layer

2014 44th European Solid State Device Research Conference (ESSDERC)
2014-09 | Conference paper
DOI:

10.1109/essderc.2014.6948835

Contributors: Maryam Olyaei; B. Gunnar Malm; Eugenio D. Litta; Per-Erik Hellstrom; Mikael Ostling
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Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology

Solid-State Electronics
2014-08 | Journal article
DOI:

10.1016/j.sse.2014.04.004

Contributors: Eugenio Dentoni Litta; Per-Erik Hellström; Christoph Henkel; Mikael Östling
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Interfacial Layer Engineering Using Thulium Silicate/Germanate for High-k/Metal Gate MOSFETs

ECS Transactions
2014-08 | Journal article
DOI:

10.1149/06406.0249ecst

Contributors: P.-E. Hellstrom; E. D. Litta; M. Ostling
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Ultra-thin film and interface analysis of high-k dielectric materials employing Time-Of-Flight Medium Energy Ion Scattering (TOF-MEIS)

Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms
2014-08 | Journal article
DOI:

10.1016/j.nimb.2014.02.063

Contributors: D. Primetzhofer; E. Dentoni Litta; A. Hallén; M.K. Linnarsson; G. Possnert
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