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Scopus Author ID: 7201392087

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Employment (2)

Barcelona Supercomputing Center: Barcelona, ES

2016-01-01 to present | Postdoctoral researcher (Computer Sciences)
Employment
Source: Self-asserted source
Lluc Alvarez

Universitat Politècnica de Catalunya: Barcelona, Catalunya, ES

2015-09 to present | Lecturer (Computer Architecture Department)
Employment
Source: Self-asserted source
Lluc Alvarez

Funding (1)

Riding on Moore's Law

Grant
European Commission (Brussels, BE)
URL: http://cordis.europa.eu/project/rcn/107241_en.html
GRANT_NUMBER: 321253
Source: Self-asserted source
Lluc Alvarez

Works (18)

Energy and Precision Evaluation of a Systolic Array Accelerator Using a Quantization Approach for Edge Computing

Electronics
2024-07 | Journal article | Author
DOI: 10.3390/electronics13142822
Contributors: Alejandra Sanchez-Flores; Jordi Fornt; Lluc Alvarez; Bartomeu Alorda
Source: check_circle
Multidisciplinary Digital Publishing Institute

Peachy Parallel Assignments (EduHPC 2018)

Proceedings of EduHPC 2018: Workshop on Education for High-Performance Computing, Held in conjunction with SC 2018: The International Conference for High Performance Computing, Networking, Storage and Analysis
2019 | Conference paper
DOI: 10.1109/EduHPC.2018.00012
EID:

2-s2.0-85063025444
Contributors: Ayguade, E.; Alvarez, L.; Banchelli, F.; Burtscher, M.; Gonzalez-Escribano, A.; Gutierrez, J.; Joiner, D.A.; Kaeli, D.; Previlon, F.; Rodriguez-Gutiez, E. et al.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Runtime-assisted cache coherence deactivation in task parallel programs

Proceedings - International Conference for High Performance Computing, Networking, Storage, and Analysis, SC 2018
2019 | Conference paper
DOI: 10.1109/SC.2018.00038
EID:

2-s2.0-85064126611
Contributors: Caheny, P.; Alvarez, L.; Valero, M.; Moreto, M.; Casas, M.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Teaching HPC systems and parallel programming with small-scale clusters

Proceedings of EduHPC 2018: Workshop on Education for High-Performance Computing, Held in conjunction with SC 2018: The International Conference for High Performance Computing, Networking, Storage and Analysis
2019 | Conference paper
DOI: 10.1109/EduHPC.2018.00004
EID:

2-s2.0-85063062660
Contributors: Alvarez, L.; Ayguade, E.; Mantovani, F.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Architectural Support for Task Dependence Management with Flexible Software Scheduling

Proceedings - International Symposium on High-Performance Computer Architecture
2018 | Conference paper
DOI: 10.1109/HPCA.2018.00033
EID:

2-s2.0-85046818144
Contributors: Castillo, E.; Alvarez, L.; Moreto, M.; Casas, M.; Vallejo, E.; Bosque, J.L.; Beivide, R.; Valero, M.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks

2018 IEEE International Symposium on Workload Characterization, IISWC 2018
2018 | Conference paper
DOI: 10.1109/IISWC.2018.8573473
EID:

2-s2.0-85060273327
Contributors: Bulla, C.; Alvarez, L.; Moreto, M.; Bertran, R.; Buyuktosunoglu, A.; Bose, P.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach

IEEE Transactions on Parallel and Distributed Systems
2018 | Journal article
DOI: 10.1109/TPDS.2017.2787123
EID:

2-s2.0-85039800616
Contributors: Caheny, P.; Alvarez, L.; Derradji, S.; Valero, M.; Moretó, M.; Casas, M.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Runtime-guided management of stacked DRAM memories in task parallel programs

Proceedings of the International Conference on Supercomputing
2018 | Conference paper
DOI: 10.1145/3205289.3205312
EID:

2-s2.0-85055849432
Contributors: Alvarez, L.; Ayguade, E.; Casas, M.; Valero, M.; Labarta, J.; Moreto, M.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

CATA: Criticality Aware Task Acceleration for Multicore Processors

Proceedings - 2016 IEEE 30th International Parallel and Distributed Processing Symposium, IPDPS 2016
2016 | Conference paper
DOI: 10.1109/IPDPS.2016.49
EID:

2-s2.0-84983283799
Contributors: Castillo, E.; Moreto, M.; Casas, M.; Alvarez, L.; Vallejo, E.; Chronaki, K.; Badia, R.; Bosque, J.L.; Beivide, R.; Ayguade, E. et al.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures

Proceedings - International Symposium on Computer Architecture
2015 | Conference paper
DOI: 10.1145/2749469.2750411
EID:

2-s2.0-84944142328
Contributors: Alvarez, L.; Vilanova, L.; Moreto, M.; Casas, M.; Gonzlez, M.; Martorell, X.; Navarro, N.; Ayguadé, E.; Valero, M.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Hardware-software coherence protocol for the coexistence of caches and local memories

IEEE Transactions on Computers
2015 | Journal article
DOI: 10.1109/TC.2013.194
EID:

2-s2.0-84919487106
Contributors: Alvarez, L.; Vilanova, L.; Gonzalez, M.; Martorell, X.; Navarro, N.; Ayguade, E.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Runtime-aware architectures

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2015 | Book
DOI: 10.1007/978-3-662-48096-0_2
EID:

2-s2.0-84944111996
Contributors: Casas, M.; Moreto, M.; Alvarez, L.; Castillo, E.; Chasapis, D.; Hayes, T.; Jaulmes, L.; Palomar, O.; Unsal, O.; Cristal, A. et al.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Runtime-Guided Management of Scratchpad Memories in Multicore Architectures

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
2015 | Conference paper
DOI: 10.1109/PACT.2015.26
EID:

2-s2.0-84975519973
Contributors: Alvarez, L.; Moreto, M.; Casas, M.; Castillo, E.; Martorell, X.; Labarta, J.; Ayguade, E.; Valero, M.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

DMA-circular: An enhanced high level programmable DMA controller for optimized management of on-chip local memories

CF '12 - Proceedings of the ACM Computing Frontiers Conference
2012 | Conference paper
DOI: 10.1145/2212908.2212925
EID:

2-s2.0-84862639331
Contributors: Vujic, N.; Alvarez, L.; Gonzalez, M.; Martorell, X.; Ayguade, E.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Hardware-software coherence protocol for the coexistence of caches and local memories

International Conference for High Performance Computing, Networking, Storage and Analysis, SC
2012 | Conference paper
DOI: 10.1109/SC.2012.61
EID:

2-s2.0-84877694295
Contributors: Alvarez, L.; Vilanova, L.; Gonzalez, M.; Martorell, X.; Navarro, N.; Ayguade, E.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Design space exploration for aggressive core replication schemes in CMPs

Proceedings of the IEEE International Symposium on High Performance Distributed Computing
2011 | Conference paper
DOI: 10.1145/1996130.1996169
EID:

2-s2.0-79960481956
Contributors: Alvarez, L.; Bertran, R.; Gonzàlez, M.; Martorell, X.; Navarro, N.; Ayguadé, E.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Adaptive and speculative memory consistency support for multi-core architectures with on-chip local memories

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2010 | Book
DOI: 10.1007/978-3-642-13374-9_15
EID:

2-s2.0-77954411293
Contributors: Vujic, N.; Alvarez, L.; Tallada, M.G.; Martorell, X.; Ayguadé, E.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier

Cetra: A trace and analysis framework for the evaluation of cell BE systems

ISPASS 2009 - International Symposium on Performance Analysis of Systems and Software
2009 | Conference paper
DOI: 10.1109/ISPASS.2009.4919637
EID:

2-s2.0-70349189978
Contributors: Merino, J.; Alvarez, L.; Gil, M.; Navarro, N.
Source: Self-asserted source
Lluc Alvarez via Scopus - Elsevier
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