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CMOS, reliability, characterization, semiconductors

Biography

Chadwin D. Young received his B.S. degree in Electrical Engineering from the Univ. of Texas at Austin in 1996 and his M.S. and Ph.D. in EE from the North Carolina State University in 1998 and 2004, respectively. In 2001, he joined SEMATECH where he completed his dissertation research on high-k gate stacks and continued this research at SEMATECH working up to Senior Member of the Technical Staff on electrical characterization and reliability methodologies for the evaluation of high-k gate stacks on current and future device architectures. He joined the Materials Science and Engineering and Electrical Engineering Departments in September 2012 where his research focus is on electrical characterization and reliability methodologies for the evaluation of future materials and devices. He is NSF CAREER Award recipient, and has authored or co-authored 325+ journal, conference and invited papers. He has served: on the management or technical program committees of IIRW, IRPS, SISC, IEDM, WoDiM, SNW; as Guest Editor for IEEE Transactions on Device and Materials Reliability; and as a peer reviewer for several journals. He is currently a Senior Member of IEEE and serves as a Device Reliability Physics Committee Member of the IEEE Electron Device Society.

Activities

Employment (7)

The University of Texas at Dallas: Richardson, TX, US

2018-09 to present | Associate Professor (Materials Science and Engineering and Electrical Engineering)
Employment
Source: Self-asserted source
Chadwin D. Young

The University of Texas at Dallas: Richardson, TX, US

2012-08 to 2018-08 | Assistant Professor (Materials Science and Engineering and Electrical Engineering)
Employment
Source: Self-asserted source
Chadwin D. Young

Sematech (United States): Albany, New York, US

2010 to 2012-08 | Senior Member of Technical Staff (Front End Processes)
Employment
Source: Self-asserted source
Chadwin D. Young

Sematech Inc Austin : Austin, TX, US

2008 to 2010 | Member of Technical Staff (Front End Processes)
Employment
Source: Self-asserted source
Chadwin D. Young

Sematech Inc Austin: Austin, TX, US

2006 to 2008 | Project Engineer (Front End Processes)
Employment
Source: Self-asserted source
Chadwin D. Young

Sematech Inc Austin: Austin, TX, US

2004 to 2006 | Post Doc (Front End Processes)
Employment
Source: Self-asserted source
Chadwin D. Young

Sematech Inc Austin: Austin, TX, US

2001 to 2004 | PhD Intern (Front End Processes)
Employment
Source: Self-asserted source
Chadwin D. Young

Education and qualifications (3)

North Carolina State University: Raleigh, North Carolina, US

1998 to 2004 | PhD (Electrical Engineering)
Education
Source: Self-asserted source
Chadwin D. Young

North Carolina State University: Raleigh, North Carolina, US

1996 to 1998 | MS (Electrical Engineering)
Education
Source: Self-asserted source
Chadwin D. Young

The University of Texas at Austin: Austin, TX, US

1990 to 1996 | BS (Electrical Engineering)
Education
Source: Self-asserted source
Chadwin D. Young

Professional activities (1)

IEEE Electron Devices Society: New York, NY, US

1996 to present | Senior Member
Membership
Source: Self-asserted source
Chadwin D. Young

Funding (5)

US-Ireland R&D Partnership: Ga2O3: Understanding Growth, Interfaces and Defects to enable next generation Electronics (GUIDE)

2022-08-15 to 2025-07-31 | Grant
Directorate for Engineering (Alexandria, US)
GRANT_NUMBER: 2154535
Source: Self-asserted source
Chadwin D. Young via DimensionsWizard

REU Site: Electronic Materials Evaluation Research for Greater Exposure to Future Technology Careers (EMERGE)

2022-03-01 to 2025-02-28 | Grant
Directorate for Mathematical & Physical Sciences (Alexandria, US)
GRANT_NUMBER: 2150281
Source: Self-asserted source
Chadwin D. Young via DimensionsWizard

MRI: Acquisition of Plasma Enhanced Atomic Layer Deposition (PEALD) for Extremely Conformal Deposition of Metal and Nitride Films on 3D-Nanostructure Devices

2019-10-01 to 2021-09-30 | Grant
Directorate for Mathematical & Physical Sciences (Arlington, US)
GRANT_NUMBER: 1919896
Source: Self-asserted source
Chadwin D. Young via DimensionsWizard

CAREER: Fundamental Electronic Device Performance and Reliability Investigation on Chalcogenide- and Oxide-based N- and P-type Materials for Large Area/Flexible Electronics

2017-03-01 to 2022-02-28 | Grant
Directorate for Engineering (Arlington, US)
GRANT_NUMBER: 1653343
Source: Self-asserted source
Chadwin D. Young via DimensionsWizard

Understanding the Nature of Interfaces in Two Dimensional Electronic Devices(UNITE)

2014-09-01 to 2018-05-31 | Grant
Directorate for Engineering (Arlington, US)
GRANT_NUMBER: 1407765
Source: Self-asserted source
Chadwin D. Young via DimensionsWizard

Peer review (1 review for 1 publication/grant)

Review activity for npj 2D materials and applications. (1)